fir_16.fit.qmsg

fir滤波器-verilog

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "33 " "Warning: Following 33 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OUT GND " "Info: Pin OUT has GND driving its datain port" {  } { { "f:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/altera/quartus/bin/pin_planner.ppl" { OUT } } } { "fft_16.v" "" { Text "C:/Documents and Settings/Administrator/桌面/fir_16/fft_16.v" 7 -1 0 } } { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { OUT } "NODE_NAME" } } { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { OUT } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "Xk_r\[0\] GND " "Info: Pin Xk_r\[0\] has GND driving its datain port" {  } { { "f:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/altera/quartus/bin/pin_planner.ppl" { Xk_r[0] } } } { "fft_16.v" "" { Text "C:/Documents and Settings/Administrator/桌面/fir_16/fft_16.v" 233 -1 0 } } { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { Xk_r[0] } "NODE_NAME" } } { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { Xk_r[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "Xk_r\[1\] GND " "Info: Pin Xk_r\[1\] has GND driving its datain port" {  } { { "f:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/altera/quartus/bin/pin_planner.ppl" { Xk_r[1] } } } { "fft_16.v" "" { Text "C:/Documents and Settings/Administrator/桌面/fir_16/fft_16.v" 233 -1 0 } } { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { Xk_r[1] } "NODE_NAME" } } { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { Xk_r[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "Xk_r\[2\] GND " "Info: Pin Xk_r\[2\] has GND driving its datain por