cmultipler.fit.rpt

复乘法器的FPGA实现

Fitter report for CMULTIPLER
Tue May 06 14:11:11 2008
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. HardCopy II Device Resource Guide
  5. Pin-Out File
  6. Fitter Resource Usage Summary
  7. Input Pins
  8. Output Pins
  9. I/O Bank Usage
 10. All Package Pins
 11. Output Pin Default Load For Reported TCO
 12. Fitter Resource Utilization by Entity
 13. Delay Chain Summary
 14. Pad To Core Delay Chain Fanout
 15. Control Signals
 16. Global & Other Fast Signals
 17. Non-Global High Fan-Out Signals
 18. Fitter DSP Block Usage Summary
 19. DSP Block Details
 20. Interconnect Usage Summary
 21. LAB Logic Elements
 22. LAB-wide Signals
 23. LAB Signals Sourced
 24. LAB Signals Sourced Out
 25. LAB Distinct Inputs
 26. I/O Rules Summary
 27. I/O Rules Details
 28. I/O Rules Matrix
 29. Fitter Device Options
 30. Advanced Data - General
 31. Advanced Data - Placement Preparation
 32. Advanced Data - Placement
 33. Advanced Data - Routing
 34. Fitter Messages
 35. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------+
; Fitter Summary                                                           ;
+-------------------------------+------------------------------------------+
; Fitter Status                 ; Successful - Tue May 06 14:11:11 2008    ;
; Quartus II Version            ; 6.1 Build 201 11/27/2006 SJ Full Version ;
; Revision Name                 ; CMULTIPLER                               ;
; Top-level Entity Name         ; CMULTIPLEX                               ;
; Family                        ; Stratix II                               ;
; Device                        ; EP2S15F484C3                             ;
; Timing Models                 ; Final                                    ;
; Logic utilization             ; 2 %                                      ;
;     Combinational ALUTs       ; 162 / 12,480 ( 1 % )                     ;
;     Dedicated logic registers ; 160 / 12,480 ( 1 % )                     ;
; Total registers               ; 160                                      ;
; Total pins                    ; 131 / 343 ( 38 % )                       ;
; Total virtual pins            ; 0                                        ;
; Total block memory bits       ; 0 / 419,328 ( 0 % )                      ;
; DSP block 9-bit elements      ; 6 / 96 ( 6 % )                           ;
; Total PLLs                    ; 0 / 6 ( 0 % )                            ;
; Total DLLs                    ; 0 / 2 ( 0 % )                            ;
+-------------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                          ;