cmultipler.sim.rpt

复乘法器的FPGA实现

; Add pins automatically to simulation output waveforms                                      ; On             ; On            ;
; Check outputs                                                                              ; Off            ; Off           ;
; Report simulation coverage                                                                 ; On             ; On            ;
; Display complete 1/0 value coverage report                                                 ; On             ; On            ;
; Display missing 1-value coverage report                                                    ; On             ; On            ;
; Display missing 0-value coverage report                                                    ; On             ; On            ;
; Detect setup and hold time violations                                                      ; Off            ; Off           ;
; Detect glitches                                                                            ; Off            ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off            ; Off           ;
; Generate Signal Activity File                                                              ; Off            ; Off           ;
; Generate VCD File for PowerPlay Power Analyzer                                             ; Off            ; Off           ;
; Group bus channels in simulation results                                                   ; Off            ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On             ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE     ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off            ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off            ;               ;
; Glitch Filtering                                                                           ; Off            ; Off           ;
+--------------------------------------------------------------------------------------------+----------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      22.81 % ;
; Total nodes checked                                 ; 459          ;
; Total output ports checked                          ; 684          ;
; Total output ports with complete 1/0-value coverage ; 156          ;
; Total output ports with no 1/0-value coverage       ; 471          ;
; Total output ports with no 1-value coverage         ; 512          ;
; Total output ports with no 0-value coverage         ; 487          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                                                 ;
+--------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                                ; Output Port Name                                                                                                              ; Output Port Type ;
+--------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+------------------+
; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[0] ; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|result[0]             ; sumout           ;
; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[0] ; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[0]~COUT ; cout             ;
; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[1] ; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|result[1]             ; sumout           ;
; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[1] ; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[1]~COUT ; cout             ;
; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[2] ; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|result[2]             ; sumout           ;
; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[2] ; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[2]~COUT ; cout             ;
; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[3] ; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|result[3]             ; sumout           ;
; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[3] ; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[3]~COUT ; cout             ;
; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[4] ; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|result[4]             ; sumout           ;
; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[4] ; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[4]~COUT ; cout             ;
; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[5] ; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|result[5]             ; sumout           ;
; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[5] ; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[5]~COUT ; cout             ;
; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[6] ; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|result[6]             ; sumout           ;
; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[6] ; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[6]~COUT ; cout             ;
; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|add_sub_cella[7] ; |CMULTIPLEX|ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_3od:auto_generated|result[7]             ; sumout           ;
; |CMULTIPLEX|ADDSUB_16_0:add1|result[0]~171                                                                               ; |CMULTIPLEX|ADDSUB_16_0:add1|result[0]~171                                                                                    ; combout          ;
; |CMULTIPLEX|ADDSUB_16_0:add1|result[1]~172                                                                               ; |CMULTIPLEX|ADDSUB_16_0:add1|result[1]~172                                                                                    ; combout          ;
; |CMULTIPLEX|ADDSUB_16_0:add1|result[2]~173                                                                               ; |CMULTIPLEX|ADDSUB_16_0:add1|result[2]~173                                                                                    ; combout          ;