cmultipler.map.eqn

复乘法器的FPGA实现

--sigbuf2[2] is sigbuf2[2]
sigbuf2[2] = DFFEAS(sigbuf1[2], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf2[3] is sigbuf2[3]
sigbuf2[3] = DFFEAS(sigbuf1[3], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf2[4] is sigbuf2[4]
sigbuf2[4] = DFFEAS(sigbuf1[4], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf2[5] is sigbuf2[5]
sigbuf2[5] = DFFEAS(sigbuf1[5], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf2[6] is sigbuf2[6]
sigbuf2[6] = DFFEAS(sigbuf1[6], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf2[7] is sigbuf2[7]
sigbuf2[7] = DFFEAS(sigbuf1[7], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf2[8] is sigbuf2[8]
sigbuf2[8] = DFFEAS(sigbuf1[8], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf2[9] is sigbuf2[9]
sigbuf2[9] = DFFEAS(sigbuf1[9], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf2[10] is sigbuf2[10]
sigbuf2[10] = DFFEAS(sigbuf1[10], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf2[11] is sigbuf2[11]
sigbuf2[11] = DFFEAS(sigbuf1[11], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf2[12] is sigbuf2[12]
sigbuf2[12] = DFFEAS(sigbuf1[12], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf2[13] is sigbuf2[13]
sigbuf2[13] = DFFEAS(sigbuf1[13], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf2[14] is sigbuf2[14]
sigbuf2[14] = DFFEAS(sigbuf1[14], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf2[15] is sigbuf2[15]
sigbuf2[15] = DFFEAS(sigbuf1[15], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf4[0] is sigbuf4[0]
sigbuf4[0] = DFFEAS(sigbuf3[0], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf4[1] is sigbuf4[1]
sigbuf4[1] = DFFEAS(sigbuf3[1], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf4[2] is sigbuf4[2]
sigbuf4[2] = DFFEAS(sigbuf3[2], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf4[3] is sigbuf4[3]
sigbuf4[3] = DFFEAS(sigbuf3[3], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf4[4] is sigbuf4[4]
sigbuf4[4] = DFFEAS(sigbuf3[4], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf4[5] is sigbuf4[5]
sigbuf4[5] = DFFEAS(sigbuf3[5], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf4[6] is sigbuf4[6]
sigbuf4[6] = DFFEAS(sigbuf3[6], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf4[7] is sigbuf4[7]
sigbuf4[7] = DFFEAS(sigbuf3[7], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf4[8] is sigbuf4[8]
sigbuf4[8] = DFFEAS(sigbuf3[8], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf4[9] is sigbuf4[9]
sigbuf4[9] = DFFEAS(sigbuf3[9], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf4[10] is sigbuf4[10]
sigbuf4[10] = DFFEAS(sigbuf3[10], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf4[11] is sigbuf4[11]
sigbuf4[11] = DFFEAS(sigbuf3[11], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf4[12] is sigbuf4[12]
sigbuf4[12] = DFFEAS(sigbuf3[12], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf4[13] is sigbuf4[13]
sigbuf4[13] = DFFEAS(sigbuf3[13], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf4[14] is sigbuf4[14]
sigbuf4[14] = DFFEAS(sigbuf3[14], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf4[15] is sigbuf4[15]
sigbuf4[15] = DFFEAS(sigbuf3[15], clk, !reset,  , clkena,  ,  ,  ,  );


--F3_result[0] is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[0]
F3_result[0]_adder_eqn = ( H1_result[15] ) + ( H2_result[15] ) + ( GND );
F3_result[0] = SUM(F3_result[0]_adder_eqn);

--F3L4 is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[0]~COUT
F3L4_adder_eqn = ( H1_result[15] ) + ( H2_result[15] ) + ( GND );
F3L4 = CARRY(F3L4_adder_eqn);


--F3_result[1] is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[1]
F3_result[1]_adder_eqn = ( H1_result[16] ) + ( H2_result[16] ) + ( F3L4 );
F3_result[1] = SUM(F3_result[1]_adder_eqn);

--F3L8 is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[1]~COUT
F3L8_adder_eqn = ( H1_result[16] ) + ( H2_result[16] ) + ( F3L4 );
F3L8 = CARRY(F3L8_adder_eqn);


--F3_result[2] is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[2]
F3_result[2]_adder_eqn = ( H1_result[17] ) + ( H2_result[17] ) + ( F3L8 );
F3_result[2] = SUM(F3_result[2]_adder_eqn);

--F3L12 is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[2]~COUT
F3L12_adder_eqn = ( H1_result[17] ) + ( H2_result[17] ) + ( F3L8 );
F3L12 = CARRY(F3L12_adder_eqn);


--F3_result[3] is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[3]
F3_result[3]_adder_eqn = ( H1_result[18] ) + ( H2_result[18] ) + ( F3L12 );
F3_result[3] = SUM(F3_result[3]_adder_eqn);

--F3L16 is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[3]~COUT
F3L16_adder_eqn = ( H1_result[18] ) + ( H2_result[18] ) + ( F3L12 );
F3L16 = CARRY(F3L16_adder_eqn);


--F3_result[4] is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[4]
F3_result[4]_adder_eqn = ( H1_result[19] ) + ( H2_result[19] ) + ( F3L16 );
F3_result[4] = SUM(F3_result[4]_adder_eqn);

--F3L20 is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[4]~COUT
F3L20_adder_eqn = ( H1_result[19] ) + ( H2_result[19] ) + ( F3L16 );
F3L20 = CARRY(F3L20_adder_eqn);


--F3_result[5] is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[5]
F3_result[5]_adder_eqn = ( H1_result[20] ) + ( H2_result[20] ) + ( F3L20 );
F3_result[5] = SUM(F3_result[5]_adder_eqn);

--F3L24 is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[5]~COUT
F3L24_adder_eqn = ( H1_result[20] ) + ( H2_result[20] ) + ( F3L20 );
F3L24 = CARRY(F3L24_adder_eqn);


--F3_result[6] is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[6]
F3_result[6]_adder_eqn = ( H1_result[21] ) + ( H2_result[21] ) + ( F3L24 );
F3_result[6] = SUM(F3_result[6]_adder_eqn);

--F3L28 is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[6]~COUT
F3L28_adder_eqn = ( H1_result[21] ) + ( H2_result[21] ) + ( F3L24 );
F3L28 = CARRY(F3L28_adder_eqn);


--F3_result[7] is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[7]
F3_result[7]_adder_eqn = ( H1_result[22] ) + ( H2_result[22] ) + ( F3L28 );
F3_result[7] = SUM(F3_result[7]_adder_eqn);

--F3L32 is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[7]~COUT
F3L32_adder_eqn = ( H1_result[22] ) + ( H2_result[22] ) + ( F3L28 );
F3L32 = CARRY(F3L32_adder_eqn);


--F3_result[8] is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[8]
F3_result[8]_adder_eqn = ( H1_result[23] ) + ( H2_result[23] ) + ( F3L32 );
F3_result[8] = SUM(F3_result[8]_adder_eqn);

--F3L36 is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[8]~COUT
F3L36_adder_eqn = ( H1_result[23] ) + ( H2_result[23] ) + ( F3L32 );
F3L36 = CARRY(F3L36_adder_eqn);


--F3_result[9] is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[9]
F3_result[9]_adder_eqn = ( H1_result[24] ) + ( H2_result[24] ) + ( F3L36 );
F3_result[9] = SUM(F3_result[9]_adder_eqn);

--F3L40 is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[9]~COUT
F3L40_adder_eqn = ( H1_result[24] ) + ( H2_result[24] ) + ( F3L36 );
F3L40 = CARRY(F3L40_adder_eqn);


--F3_result[10] is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[10]
F3_result[10]_adder_eqn = ( H1_result[25] ) + ( H2_result[25] ) + ( F3L40 );
F3_result[10] = SUM(F3_result[10]_adder_eqn);

--F3L44 is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[10]~COUT
F3L44_adder_eqn = ( H1_result[25] ) + ( H2_result[25] ) + ( F3L40 );
F3L44 = CARRY(F3L44_adder_eqn);


--F3_result[11] is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[11]
F3_result[11]_adder_eqn = ( H1_result[26] ) + ( H2_result[26] ) + ( F3L44 );
F3_result[11] = SUM(F3_result[11]_adder_eqn);

--F3L48 is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[11]~COUT
F3L48_adder_eqn = ( H1_result[26] ) + ( H2_result[26] ) + ( F3L44 );
F3L48 = CARRY(F3L48_adder_eqn);


--F3_result[12] is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[12]
F3_result[12]_adder_eqn = ( H1_result[27] ) + ( H2_result[27] ) + ( F3L48 );
F3_result[12] = SUM(F3_result[12]_adder_eqn);

--F3L52 is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[12]~COUT
F3L52_adder_eqn = ( H1_result[27] ) + ( H2_result[27] ) + ( F3L48 );
F3L52 = CARRY(F3L52_adder_eqn);


--F3_result[13] is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[13]
F3_result[13]_adder_eqn = ( H1_result[28] ) + ( H2_result[28] ) + ( F3L52 );
F3_result[13] = SUM(F3_result[13]_adder_eqn);

--F3L56 is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[13]~COUT
F3L56_adder_eqn = ( H1_result[28] ) + ( H2_result[28] ) + ( F3L52 );
F3L56 = CARRY(F3L56_adder_eqn);


--F3_result[14] is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[14]
F3_result[14]_adder_eqn = ( H1_result[29] ) + ( H2_result[29] ) + ( F3L56 );
F3_result[14] = SUM(F3_result[14]_adder_eqn);

--F3L60 is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[14]~COUT
F3L60_adder_eqn = ( H1_result[29] ) + ( H2_result[29] ) + ( F3L56 );
F3L60 = CARRY(F3L60_adder_eqn);


--F3_result[15] is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[15]
F3_result[15]_adder_eqn = ( H1_result[30] ) + ( H2_result[30] ) + ( F3L60 );
F3_result[15] = SUM(F3_result[15]_adder_eqn);

--F3L64 is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[15]~COUT
F3L64_adder_eqn = ( H1_result[30] ) + ( H2_result[30] ) + ( F3L60 );
F3L64 = CARRY(F3L64_adder_eqn);


--F3_result[16] is ADDSUB_16_0:add3|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[16]
F3_result[16]_adder_eqn = ( H1_result[30] ) + ( H2_result[30] ) + ( F3L64 );
F3_result[16] = SUM(F3_result[16]_adder_eqn);


--B3L1 is ADDSUB_16_0:add3|result[0]~731
B3L1 = !F3_result[0] & F3_result[15] & !F3_result[16] # F3_result[0] & (!F3_result[16] # F3_result[15]);


--B3L15 is ADDSUB_16_0:add3|result[14]~732
B3L15 = !F3_result[14] & F3_result[15] & !F3_result[16] # F3_result[14] & (!F3_result[16] # F3_result[15]);


--B3L14 is ADDSUB_16_0:add3|result[13]~733
B3L14 = !F3_result[13] & F3_result[15] & !F3_result[16] # F3_result[13] & (!F3_result[16] # F3_result[15]);


--B3L13 is ADDSUB_16_0:add3|result[12]~734
B3L13 = !F3_result[12] & F3_result[15] & !F3_result[16] # F3_result[12] & (!F3_result[16] # F3_result[15]);


--B3L12 is ADDSUB_16_0:add3|result[11]~735
B3L12 = !F3_result[11] & F3_result[15] & !F3_result[16] # F3_result[11] & (!F3_result[16] # F3_result[15]);


--B3L11 is ADDSUB_16_0:add3|result[10]~736
B3L11 = !F3_result[10] & F3_result[15] & !F3_result[16] # F3_result[10] & (!F3_result[16] # F3_result[15]);


--B3L10 is ADDSUB_16_0:add3|result[9]~737
B3L10 = !F3_result[9] & F3_result[15] & !F3_result[16] # F3_result[9] & (!F3_result[16] # F3_result[15]);


--B3L9 is ADDSUB_16_0:add3|result[8]~738
B3L9 = !F3_result[8] & F3_result[15] & !F3_result[16] # F3_result[8] & (!F3_result[16] # F3_result[15]);


--B3L8 is ADDSUB_16_0:add3|result[7]~739
B3L8 = !F3_result[7] & F3_result[15] & !F3_result[16] # F3_result[7] & (!F3_result[16] # F3_result[15]);


--B3L7 is ADDSUB_16_0:add3|result[6]~740
B3L7 = !F3_result[6] & F3_result[15] & !F3_result[16] # F3_result[6] & (!F3_result[16] # F3_result[15]);


--B3L6 is ADDSUB_16_0:add3|result[5]~741
B3L6 = !F3_result[5] & F3_result[15] & !F3_result[16] # F3_result[5] & (!F3_result[16] # F3_result[15]);


--B3L5 is ADDSUB_16_0:add3|result[4]~742
B3L5 = !F3_result[4] & F3_result[15] & !F3_result[16] # F3_result[4] & (!F3_result[16] # F3_result[15]);


--B3L4 is ADDSUB_16_0:add3|result[3]~743
B3L4 = !F3_result[3] & F3_result[15] & !F3_result[16] # F3_result[3] & (!F3_result[16] # F3_result[15]);


--B3L3 is ADDSUB_16_0:add3|result[2]~