cmultipler.map.eqn

复乘法器的FPGA实现

sigbuf5[1] = DFFEAS(B3L2, clk, !reset,  , clkena,  ,  ,  ,  );


--H1_result[15] is MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[15]
--DSP Block Operation Mode: Simple Multiplier (18-bit)
H1_result[15] = H1L16Q;

--H1_result[16] is MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[16]
H1_result[16] = H1L17Q;

--H1_result[17] is MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[17]
H1_result[17] = H1L18Q;

--H1_result[18] is MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[18]
H1_result[18] = H1L19Q;

--H1_result[19] is MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[19]
H1_result[19] = H1L20Q;

--H1_result[20] is MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[20]
H1_result[20] = H1L21Q;

--H1_result[21] is MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[21]
H1_result[21] = H1L22Q;

--H1_result[22] is MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[22]
H1_result[22] = H1L23Q;

--H1_result[23] is MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[23]
H1_result[23] = H1L24Q;

--H1_result[24] is MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[24]
H1_result[24] = H1L25Q;

--H1_result[25] is MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[25]
H1_result[25] = H1L26Q;

--H1_result[26] is MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[26]
H1_result[26] = H1L27Q;

--H1_result[27] is MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[27]
H1_result[27] = H1L28Q;

--H1_result[28] is MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[28]
H1_result[28] = H1L29Q;

--H1_result[29] is MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[29]
H1_result[29] = H1L30Q;

--H1_result[30] is MULTP:mult1|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[30]
H1_result[30] = H1L31Q;


--H2_result[15] is MULTP:mult2|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[15]
--DSP Block Operation Mode: Simple Multiplier (18-bit)
H2_result[15] = H2L16Q;

--H2_result[16] is MULTP:mult2|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[16]
H2_result[16] = H2L17Q;

--H2_result[17] is MULTP:mult2|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[17]
H2_result[17] = H2L18Q;

--H2_result[18] is MULTP:mult2|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[18]
H2_result[18] = H2L19Q;

--H2_result[19] is MULTP:mult2|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[19]
H2_result[19] = H2L20Q;

--H2_result[20] is MULTP:mult2|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[20]
H2_result[20] = H2L21Q;

--H2_result[21] is MULTP:mult2|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[21]
H2_result[21] = H2L22Q;

--H2_result[22] is MULTP:mult2|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[22]
H2_result[22] = H2L23Q;

--H2_result[23] is MULTP:mult2|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[23]
H2_result[23] = H2L24Q;

--H2_result[24] is MULTP:mult2|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[24]
H2_result[24] = H2L25Q;

--H2_result[25] is MULTP:mult2|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[25]
H2_result[25] = H2L26Q;

--H2_result[26] is MULTP:mult2|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[26]
H2_result[26] = H2L27Q;

--H2_result[27] is MULTP:mult2|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[27]
H2_result[27] = H2L28Q;

--H2_result[28] is MULTP:mult2|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[28]
H2_result[28] = H2L29Q;

--H2_result[29] is MULTP:mult2|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[29]
H2_result[29] = H2L30Q;

--H2_result[30] is MULTP:mult2|lpm_mult:lpm_mult_component|mult_2su:auto_generated|result[30]
H2_result[30] = H2L31Q;


--F4L5 is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[0]~6
F4L5_adder_eqn = ( VCC ) + ( VCC ) + ( GND );
F4L5 = CARRY(F4L5_adder_eqn);


--F4_result[0] is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[0]
F4_result[0]_adder_eqn = ( H1_result[15] ) + ( !H2_result[15] ) + ( F4L5 );
F4_result[0] = SUM(F4_result[0]_adder_eqn);

--F4L8 is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[0]~COUT
F4L8_adder_eqn = ( H1_result[15] ) + ( !H2_result[15] ) + ( F4L5 );
F4L8 = CARRY(F4L8_adder_eqn);


--F4_result[1] is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[1]
F4_result[1]_adder_eqn = ( H1_result[16] ) + ( !H2_result[16] ) + ( F4L8 );
F4_result[1] = SUM(F4_result[1]_adder_eqn);

--F4L12 is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[1]~COUT
F4L12_adder_eqn = ( H1_result[16] ) + ( !H2_result[16] ) + ( F4L8 );
F4L12 = CARRY(F4L12_adder_eqn);


--F4_result[2] is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[2]
F4_result[2]_adder_eqn = ( H1_result[17] ) + ( !H2_result[17] ) + ( F4L12 );
F4_result[2] = SUM(F4_result[2]_adder_eqn);

--F4L16 is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[2]~COUT
F4L16_adder_eqn = ( H1_result[17] ) + ( !H2_result[17] ) + ( F4L12 );
F4L16 = CARRY(F4L16_adder_eqn);


--F4_result[3] is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[3]
F4_result[3]_adder_eqn = ( H1_result[18] ) + ( !H2_result[18] ) + ( F4L16 );
F4_result[3] = SUM(F4_result[3]_adder_eqn);

--F4L20 is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[3]~COUT
F4L20_adder_eqn = ( H1_result[18] ) + ( !H2_result[18] ) + ( F4L16 );
F4L20 = CARRY(F4L20_adder_eqn);


--F4_result[4] is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[4]
F4_result[4]_adder_eqn = ( H1_result[19] ) + ( !H2_result[19] ) + ( F4L20 );
F4_result[4] = SUM(F4_result[4]_adder_eqn);

--F4L24 is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[4]~COUT
F4L24_adder_eqn = ( H1_result[19] ) + ( !H2_result[19] ) + ( F4L20 );
F4L24 = CARRY(F4L24_adder_eqn);


--F4_result[5] is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[5]
F4_result[5]_adder_eqn = ( H1_result[20] ) + ( !H2_result[20] ) + ( F4L24 );
F4_result[5] = SUM(F4_result[5]_adder_eqn);

--F4L28 is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[5]~COUT
F4L28_adder_eqn = ( H1_result[20] ) + ( !H2_result[20] ) + ( F4L24 );
F4L28 = CARRY(F4L28_adder_eqn);


--F4_result[6] is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[6]
F4_result[6]_adder_eqn = ( H1_result[21] ) + ( !H2_result[21] ) + ( F4L28 );
F4_result[6] = SUM(F4_result[6]_adder_eqn);

--F4L32 is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[6]~COUT
F4L32_adder_eqn = ( H1_result[21] ) + ( !H2_result[21] ) + ( F4L28 );
F4L32 = CARRY(F4L32_adder_eqn);


--F4_result[7] is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[7]
F4_result[7]_adder_eqn = ( H1_result[22] ) + ( !H2_result[22] ) + ( F4L32 );
F4_result[7] = SUM(F4_result[7]_adder_eqn);

--F4L36 is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[7]~COUT
F4L36_adder_eqn = ( H1_result[22] ) + ( !H2_result[22] ) + ( F4L32 );
F4L36 = CARRY(F4L36_adder_eqn);


--F4_result[8] is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[8]
F4_result[8]_adder_eqn = ( H1_result[23] ) + ( !H2_result[23] ) + ( F4L36 );
F4_result[8] = SUM(F4_result[8]_adder_eqn);

--F4L40 is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[8]~COUT
F4L40_adder_eqn = ( H1_result[23] ) + ( !H2_result[23] ) + ( F4L36 );
F4L40 = CARRY(F4L40_adder_eqn);


--F4_result[9] is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[9]
F4_result[9]_adder_eqn = ( H1_result[24] ) + ( !H2_result[24] ) + ( F4L40 );
F4_result[9] = SUM(F4_result[9]_adder_eqn);

--F4L44 is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[9]~COUT
F4L44_adder_eqn = ( H1_result[24] ) + ( !H2_result[24] ) + ( F4L40 );
F4L44 = CARRY(F4L44_adder_eqn);


--F4_result[10] is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[10]
F4_result[10]_adder_eqn = ( H1_result[25] ) + ( !H2_result[25] ) + ( F4L44 );
F4_result[10] = SUM(F4_result[10]_adder_eqn);

--F4L48 is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[10]~COUT
F4L48_adder_eqn = ( H1_result[25] ) + ( !H2_result[25] ) + ( F4L44 );
F4L48 = CARRY(F4L48_adder_eqn);


--F4_result[11] is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[11]
F4_result[11]_adder_eqn = ( H1_result[26] ) + ( !H2_result[26] ) + ( F4L48 );
F4_result[11] = SUM(F4_result[11]_adder_eqn);

--F4L52 is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[11]~COUT
F4L52_adder_eqn = ( H1_result[26] ) + ( !H2_result[26] ) + ( F4L48 );
F4L52 = CARRY(F4L52_adder_eqn);


--F4_result[12] is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[12]
F4_result[12]_adder_eqn = ( H1_result[27] ) + ( !H2_result[27] ) + ( F4L52 );
F4_result[12] = SUM(F4_result[12]_adder_eqn);

--F4L56 is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[12]~COUT
F4L56_adder_eqn = ( H1_result[27] ) + ( !H2_result[27] ) + ( F4L52 );
F4L56 = CARRY(F4L56_adder_eqn);


--F4_result[13] is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[13]
F4_result[13]_adder_eqn = ( H1_result[28] ) + ( !H2_result[28] ) + ( F4L56 );
F4_result[13] = SUM(F4_result[13]_adder_eqn);

--F4L60 is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[13]~COUT
F4L60_adder_eqn = ( H1_result[28] ) + ( !H2_result[28] ) + ( F4L56 );
F4L60 = CARRY(F4L60_adder_eqn);


--F4_result[14] is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[14]
F4_result[14]_adder_eqn = ( H1_result[29] ) + ( !H2_result[29] ) + ( F4L60 );
F4_result[14] = SUM(F4_result[14]_adder_eqn);

--F4L64 is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[14]~COUT
F4L64_adder_eqn = ( H1_result[29] ) + ( !H2_result[29] ) + ( F4L60 );
F4L64 = CARRY(F4L64_adder_eqn);


--F4_result[15] is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[15]
F4_result[15]_adder_eqn = ( H1_result[30] ) + ( !H2_result[30] ) + ( F4L64 );
F4_result[15] = SUM(F4_result[15]_adder_eqn);

--F4L68 is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[15]~COUT
F4L68_adder_eqn = ( H1_result[30] ) + ( !H2_result[30] ) + ( F4L64 );
F4L68 = CARRY(F4L68_adder_eqn);


--F4_result[16] is ADDSUB_16_0:sub1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[16]
F4_result[16]_adder_eqn = ( H1_result[30] ) + ( !H2_result[30] ) + ( F4L68 );
F4_result[16] = SUM(F4_result[16]_adder_eqn);


--B4L1 is ADDSUB_16_0:sub1|result[0]~731
B4L1 = !F4_result[0] & F4_result[15] & !F4_result[16] # F4_result[0] & (!F4_result[16] # F4_result[15]);


--B4L2 is ADDSUB_16_0:sub1|result[1]~732
B4L2 = !F4_result[1] & F4_result[15] & !F4_result[16] # F4_result[1] & (!F4_result[16] # F4_result[15]);


--B4L3 is ADDSUB_16_0:sub1|result[2]~733
B4L3 = !F4_result[2] & F4_result[15] & !F4_result[16] # F4_result[2] & (!F4_result[16] # F4_result[15]);


--B4L4 is ADDSUB_16_0:sub1|result[3]~734
B4L4 = !F4_result[3] & F4_result[15] & !F4_result[16] # F4_result[3] & (!F4_result[16] # F4_result[15]);


--B4L5 is ADDSUB_16_0:sub1|result[4]~735
B4L5 = !F4_result[4] & F4_result[15] & !F4_result[16] # F4_result[4] & (!F4_result[16] # F4_result[15]);


--B4L6 is ADDSUB_16_0:sub1|result[5]~736
B4L6 = !F4_result[5] & F4_result[15] & !F4_result[16] # F4_result[5] & (!F4_result[16] # F4_result[15]);


--B4L7 is ADDSUB_16_0:sub1|result[6]~737
B4L7 = !F4_result[6] & F4_result[15] & !F4_result[16] # F4_result[6] & (!F4_result[16] # F4_result[15]);


--B4L8 is ADDSUB_16_0:sub1|result[7]~738
B4L8 = !F4_result[7] & F4_result[15] & !F4_result[16] # F4_result[7] & (!F4_result[16] # F4_result[15]);


--B4L9 is ADDSUB_16_0:sub1|result[8]~739
B4L9 = !F4_result[8] & F4_result[15] & !F4_result[16] # F4_result[8] & (!F4_result[16] # F4_result[15]);


--B4L10 is ADDSUB_16_0:sub1|result[9]~740
B4L10 = !F4_result[9] & F4_result[15] & !F4_result[16] # F4_result[9] & (!F4_result[16] # F4_result[15]);


--B4L11 is ADDSUB_16_0:sub1|result[10]~741
B4L11 = !F4_result[10] & F4_result[15] & !F4_result[16] # F4_result[10] & (!F4_result[16] # F4_result[15]);


--B4L12 is ADDSUB_16_0:sub1|result[11]~742
B4L12 = !F4_result[11] & F4_result[15] & !F4_result[16] # F4_result[11] & (!F4_result[16] # F4_result[15]);


--B4L13 is ADDSUB_16_0:sub1|result[12]~743
B4L13 = !F4_result[12] & F4_result[15] & !F4_result[16] # F4_result[12] & (!F4_result[16] # F4_result[15]);


--B4L14 is ADDSUB_16_0:sub1|result[13]~744
B4L14 = !F4_result[13] & F4_result[15] & !F4_result[16] # F4_result[13] & (!F4_result[16] # F4_result[15]);


--B4L15 is ADDSUB_16_0:sub1|result[14]~745
B4L15 = !F4_result[14] & F4_result[15] & !F4_result[16] # F4_result[14] & (!F4_result[16] # F4_result[15]);


--sigbuf2[0] is sigbuf2[0]
sigbuf2[0] = DFFEAS(sigbuf1[0], clk, !reset,  , clkena,  ,  ,  ,  );


--sigbuf2[1] is sigbuf2[1]
sigbuf2[1] = DFFEAS(sigbuf1[1], clk, !reset,  , clkena,  ,  ,  ,  );