cmultipler.map.eqn

复乘法器的FPGA实现

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--A1L39Q is iout[0]~reg0
A1L39Q = DFFEAS(sigbuf8[0], clk, !reset,  , clkena,  ,  ,  ,  );


--A1L41Q is iout[1]~reg0
A1L41Q = DFFEAS(sigbuf8[1], clk, !reset,  , clkena,  ,  ,  ,  );


--A1L43Q is iout[2]~reg0
A1L43Q = DFFEAS(sigbuf8[2], clk, !reset,  , clkena,  ,  ,  ,  );


--A1L45Q is iout[3]~reg0
A1L45Q = DFFEAS(sigbuf8[3], clk, !reset,  , clkena,  ,  ,  ,  );


--A1L47Q is iout[4]~reg0
A1L47Q = DFFEAS(sigbuf8[4], clk, !reset,  , clkena,  ,  ,  ,  );


--A1L49Q is iout[5]~reg0
A1L49Q = DFFEAS(sigbuf8[5], clk, !reset,  , clkena,  ,  ,  ,  );


--A1L51Q is iout[6]~reg0
A1L51Q = DFFEAS(sigbuf8[6], clk, !reset,  , clkena,  ,  ,  ,  );


--A1L53Q is iout[7]~reg0
A1L53Q = DFFEAS(sigbuf8[7], clk, !reset,  , clkena,  ,  ,  ,  );


--A1L55Q is iout[8]~reg0
A1L55Q = DFFEAS(sigbuf8[8], clk, !reset,  , clkena,  ,  ,  ,  );


--A1L57Q is iout[9]~reg0
A1L57Q = DFFEAS(sigbuf8[9], clk, !reset,  , clkena,  ,  ,  ,  );


--A1L59Q is iout[10]~reg0
A1L59Q = DFFEAS(sigbuf8[10], clk, !reset,  , clkena,  ,  ,  ,  );


--A1L61Q is iout[11]~reg0
A1L61Q = DFFEAS(sigbuf8[11], clk, !reset,  , clkena,  ,  ,  ,  );


--A1L63Q is iout[12]~reg0
A1L63Q = DFFEAS(sigbuf8[12], clk, !reset,  , clkena,  ,  ,  ,  );


--A1L65Q is iout[13]~reg0
A1L65Q = DFFEAS(sigbuf8[13], clk, !reset,  , clkena,  ,  ,  ,  );


--A1L67Q is iout[14]~reg0
A1L67Q = DFFEAS(sigbuf8[14], clk, !reset,  , clkena,  ,  ,  ,  );


--A1L69Q is iout[15]~reg0
A1L69Q = DFFEAS(sigbuf8[15], clk, !reset,  , clkena,  ,  ,  ,  );


--A1L106Q is qout[0]~reg0
A1L106Q = DFFEAS(B5L1, clk, !reset,  , clkena,  ,  ,  ,  );


--A1L108Q is qout[1]~reg0
A1L108Q = DFFEAS(B5L2, clk, !reset,  , clkena,  ,  ,  ,  );


--A1L110Q is qout[2]~reg0
A1L110Q = DFFEAS(B5L3, clk, !reset,  , clkena,  ,  ,  ,  );


--A1L112Q is qout[3]~reg0
A1L112Q = DFFEAS(B5L4, clk, !reset,  , clkena,  ,  ,  ,  );


--A1L114Q is qout[4]~reg0
A1L114Q = DFFEAS(B5L5, clk, !reset,  , clkena,  ,  ,  ,  );


--A1L116Q is qout[5]~reg0
A1L116Q = DFFEAS(B5L6, clk, !reset,  , clkena,  ,  ,  ,  );


--A1L118Q is qout[6]~reg0
A1L118Q = DFFEAS(B5L7, clk, !reset,  , clkena,  ,  ,  ,  );


--A1L120Q is qout[7]~reg0
A1L120Q = DFFEAS(B5L8, clk, !reset,  , clkena,  ,  ,  ,  );


--A1L122Q is qout[8]~reg0
A1L122Q = DFFEAS(B5L9, clk, !reset,  , clkena,  ,  ,  ,  );


--A1L124Q is qout[9]~reg0
A1L124Q = DFFEAS(B5L10, clk, !reset,  , clkena,  ,  ,  ,  );


--A1L126Q is qout[10]~reg0
A1L126Q = DFFEAS(B5L11, clk, !reset,  , clkena,  ,  ,  ,  );


--A1L128Q is qout[11]~reg0
A1L128Q = DFFEAS(B5L12, clk, !reset,  , clkena,  ,  ,  ,  );


--A1L130Q is qout[12]~reg0
A1L130Q = DFFEAS(B5L13, clk, !reset,  , clkena,  ,  ,  ,  );


--A1L132Q is qout[13]~reg0
A1L132Q = DFFEAS(B5L14, clk, !reset,  , clkena,  ,  ,  ,  );


--A1L134Q is qout[14]~reg0
A1L134Q = DFFEAS(B5L15, clk, !reset,  , clkena,  ,  ,  ,  );


--A1L136Q is qout[15]~reg0
A1L136Q = DFFEAS(F5_result[16], clk, !reset,  , clkena,  ,  ,  ,  );


--F1_result[0] is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[0]
F1_result[0]_adder_eqn = ( ia[0] ) + ( qa[0] ) + ( GND );
F1_result[0] = SUM(F1_result[0]_adder_eqn);

--F1L4 is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[0]~COUT
F1L4_adder_eqn = ( ia[0] ) + ( qa[0] ) + ( GND );
F1L4 = CARRY(F1L4_adder_eqn);


--F1_result[1] is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[1]
F1_result[1]_adder_eqn = ( ia[1] ) + ( qa[1] ) + ( F1L4 );
F1_result[1] = SUM(F1_result[1]_adder_eqn);

--F1L8 is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[1]~COUT
F1L8_adder_eqn = ( ia[1] ) + ( qa[1] ) + ( F1L4 );
F1L8 = CARRY(F1L8_adder_eqn);


--F1_result[2] is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[2]
F1_result[2]_adder_eqn = ( ia[2] ) + ( qa[2] ) + ( F1L8 );
F1_result[2] = SUM(F1_result[2]_adder_eqn);

--F1L12 is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[2]~COUT
F1L12_adder_eqn = ( ia[2] ) + ( qa[2] ) + ( F1L8 );
F1L12 = CARRY(F1L12_adder_eqn);


--F1_result[3] is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[3]
F1_result[3]_adder_eqn = ( ia[3] ) + ( qa[3] ) + ( F1L12 );
F1_result[3] = SUM(F1_result[3]_adder_eqn);

--F1L16 is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[3]~COUT
F1L16_adder_eqn = ( ia[3] ) + ( qa[3] ) + ( F1L12 );
F1L16 = CARRY(F1L16_adder_eqn);


--F1_result[4] is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[4]
F1_result[4]_adder_eqn = ( ia[4] ) + ( qa[4] ) + ( F1L16 );
F1_result[4] = SUM(F1_result[4]_adder_eqn);

--F1L20 is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[4]~COUT
F1L20_adder_eqn = ( ia[4] ) + ( qa[4] ) + ( F1L16 );
F1L20 = CARRY(F1L20_adder_eqn);


--F1_result[5] is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[5]
F1_result[5]_adder_eqn = ( ia[5] ) + ( qa[5] ) + ( F1L20 );
F1_result[5] = SUM(F1_result[5]_adder_eqn);

--F1L24 is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[5]~COUT
F1L24_adder_eqn = ( ia[5] ) + ( qa[5] ) + ( F1L20 );
F1L24 = CARRY(F1L24_adder_eqn);


--F1_result[6] is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[6]
F1_result[6]_adder_eqn = ( ia[6] ) + ( qa[6] ) + ( F1L24 );
F1_result[6] = SUM(F1_result[6]_adder_eqn);

--F1L28 is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[6]~COUT
F1L28_adder_eqn = ( ia[6] ) + ( qa[6] ) + ( F1L24 );
F1L28 = CARRY(F1L28_adder_eqn);


--F1_result[7] is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[7]
F1_result[7]_adder_eqn = ( ia[7] ) + ( qa[7] ) + ( F1L28 );
F1_result[7] = SUM(F1_result[7]_adder_eqn);

--F1L32 is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[7]~COUT
F1L32_adder_eqn = ( ia[7] ) + ( qa[7] ) + ( F1L28 );
F1L32 = CARRY(F1L32_adder_eqn);


--F1_result[8] is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[8]
F1_result[8]_adder_eqn = ( ia[8] ) + ( qa[8] ) + ( F1L32 );
F1_result[8] = SUM(F1_result[8]_adder_eqn);

--F1L36 is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[8]~COUT
F1L36_adder_eqn = ( ia[8] ) + ( qa[8] ) + ( F1L32 );
F1L36 = CARRY(F1L36_adder_eqn);


--F1_result[9] is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[9]
F1_result[9]_adder_eqn = ( ia[9] ) + ( qa[9] ) + ( F1L36 );
F1_result[9] = SUM(F1_result[9]_adder_eqn);

--F1L40 is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[9]~COUT
F1L40_adder_eqn = ( ia[9] ) + ( qa[9] ) + ( F1L36 );
F1L40 = CARRY(F1L40_adder_eqn);


--F1_result[10] is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[10]
F1_result[10]_adder_eqn = ( ia[10] ) + ( qa[10] ) + ( F1L40 );
F1_result[10] = SUM(F1_result[10]_adder_eqn);

--F1L44 is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[10]~COUT
F1L44_adder_eqn = ( ia[10] ) + ( qa[10] ) + ( F1L40 );
F1L44 = CARRY(F1L44_adder_eqn);


--F1_result[11] is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[11]
F1_result[11]_adder_eqn = ( ia[11] ) + ( qa[11] ) + ( F1L44 );
F1_result[11] = SUM(F1_result[11]_adder_eqn);

--F1L48 is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[11]~COUT
F1L48_adder_eqn = ( ia[11] ) + ( qa[11] ) + ( F1L44 );
F1L48 = CARRY(F1L48_adder_eqn);


--F1_result[12] is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[12]
F1_result[12]_adder_eqn = ( ia[12] ) + ( qa[12] ) + ( F1L48 );
F1_result[12] = SUM(F1_result[12]_adder_eqn);

--F1L52 is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[12]~COUT
F1L52_adder_eqn = ( ia[12] ) + ( qa[12] ) + ( F1L48 );
F1L52 = CARRY(F1L52_adder_eqn);


--F1_result[13] is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[13]
F1_result[13]_adder_eqn = ( ia[13] ) + ( qa[13] ) + ( F1L52 );
F1_result[13] = SUM(F1_result[13]_adder_eqn);

--F1L56 is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[13]~COUT
F1L56_adder_eqn = ( ia[13] ) + ( qa[13] ) + ( F1L52 );
F1L56 = CARRY(F1L56_adder_eqn);


--F1_result[14] is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[14]
F1_result[14]_adder_eqn = ( ia[14] ) + ( qa[14] ) + ( F1L56 );
F1_result[14] = SUM(F1_result[14]_adder_eqn);

--F1L60 is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[14]~COUT
F1L60_adder_eqn = ( ia[14] ) + ( qa[14] ) + ( F1L56 );
F1L60 = CARRY(F1L60_adder_eqn);


--F1_result[15] is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[15]
F1_result[15]_adder_eqn = ( ia[15] ) + ( qa[15] ) + ( F1L60 );
F1_result[15] = SUM(F1_result[15]_adder_eqn);

--F1L64 is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|add_sub_cella[15]~COUT
F1L64_adder_eqn = ( ia[15] ) + ( qa[15] ) + ( F1L60 );
F1L64 = CARRY(F1L64_adder_eqn);


--F1_result[16] is ADDSUB_16_0:add1|ADDSUB:addsub|lpm_add_sub:lpm_add_sub_component|add_sub_4od:auto_generated|result[16]
F1_result[16]_adder_eqn = ( ia[15] ) + ( qa[15] ) + ( F1L64 );
F1_result[16] = SUM(F1_result[16]_adder_eqn);


--B1L1 is ADDSUB_16_0:add1|result[0]~731
B1L1 = !F1_result[0] & F1_result[15] & !F1_result[16] # F1_result[0] & (!F1_result[16] # F1_result[15]);


--B1L2 is ADDSUB_16_0:add1|result[1]~732
B1L2 = !F1_result[1] & F1_result[15] & !F1_result[16] # F1_result[1] & (!F1_result[16] # F1_result[15]);


--B1L3 is ADDSUB_16_0:add1|result[2]~733
B1L3 = !F1_result[2] & F1_result[15] & !F1_result[16] # F1_result[2] & (!F1_result[16] # F1_result[15]);


--B1L4 is ADDSUB_16_0:add1|result[3]~734
B1L4 = !F1_result[3] & F1_result[15] & !F1_result[16] # F1_result[3] & (!F1_result[16] # F1_result[15]);


--B1L5 is ADDSUB_16_0:add1|result[4]~735
B1L5 = !F1_result[4] & F1_result[15] & !F1_result[16] # F1_result[4] & (!F1_result[16] # F1_result[15]);


--B1L6 is ADDSUB_16_0:add1|result[5]~736
B1L6 = !F1_result[5] & F1_result[15] & !F1_result[16] # F1_result[5] & (!F1_result[16] # F1_result[15]);


--B1L7 is ADDSUB_16_0:add1|result[6]~737
B1L7 = !F1_result[6] & F1_result[15] & !F1_result[16] # F1_result[6] & (!F1_result[16] # F1_result[15]);


--B1L8 is ADDSUB_16_0:add1|result[7]~738
B1L8 = !F1_result[7] & F1_result[15] & !F1_result[16] # F1_result[7] & (!F1_result[16] # F1_result[15]);


--B1L9 is ADDSUB_16_0:add1|result[8]~739
B1L9 = !F1_result[8] & F1_result[15] & !F1_result[16] # F1_result[8] & (!F1_result[16] # F1_result[15]);