div5.map.rpt

利用VHDL语言描述的5分频器（改变程序中m1,m2值

; Auto RAM to Logic Cell Conversion                            ; Off                ; Off                ;
; Auto Resource Sharing                                        ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                           ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                           ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives            ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report           ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                           ; Off                ; Off                ;
; Synchronization Register Chain Length                        ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                 ; Normal compilation ; Normal compilation ;
; HDL message level                                            ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages              ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report     ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100                ; 100                ;
; Clock MUX Protection                                         ; On                 ; On                 ;
; Block Design Naming                                          ; Auto               ; Auto               ;
; SDC constraint protection                                    ; Off                ; Off                ;
; Synthesis Effort                                             ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On                 ; On                 ;
+--------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                              ;
+----------------------------------+-----------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; div5.vhd                         ; yes             ; User VHDL File  ; E:/FPGA/div5/div5.vhd        ;
+----------------------------------+-----------------+-----------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 9     ;
;                                             ;       ;
; Total combinational functions               ; 9     ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 2     ;
;     -- 3 input functions                    ; 4     ;
;     -- <=2 input functions                  ; 3     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 9     ;
;     -- arithmetic mode                      ; 0     ;
;                                             ;       ;
; Total registers                             ; 8     ;
;     -- Dedicated logic registers            ; 8     ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 2     ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 8     ;
; Total fan-out                               ; 43    ;
; Average fan-out                             ; 2.26  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |div5                      ; 9 (9)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 2    ; 0            ; |div5               ;              ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 8     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition
    Info: Processing started: Mon Nov 17 11:47:50 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off div5 -c div5
Info: Found 2 design units, including 1 entities, in source file div5.vhd
    Info: Found design unit 1: div5-one
    Info: Found entity 1: div5
Warning: Can't analyze file -- file E:/FPGA/div5/div5.bdf is missing
Info: Elaborating entity "div5" for the top level hierarchy
Info: Implemented 11 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 9 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 181 megabytes
    Info: Processing ended: Mon Nov 17 11:47:56 2008
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:03