div5.tan.rpt

利用VHDL语言描述的5分频器（改变程序中m1,m2值

; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[2]   ; clk_temp1 ; clk        ; clk      ; None                        ; None                      ; 1.469 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[2]   ; clk_temp2 ; clk        ; clk      ; None                        ; None                      ; 1.241 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[2]   ; cnt2[0]   ; clk        ; clk      ; None                        ; None                      ; 1.192 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[0]   ; clk_temp2 ; clk        ; clk      ; None                        ; None                      ; 1.189 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[0]   ; cnt2[2]   ; clk        ; clk      ; None                        ; None                      ; 1.184 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[2]   ; cnt1[0]   ; clk        ; clk      ; None                        ; None                      ; 1.176 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[1]   ; cnt1[2]   ; clk        ; clk      ; None                        ; None                      ; 1.171 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[1]   ; cnt1[0]   ; clk        ; clk      ; None                        ; None                      ; 1.060 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[1]   ; clk_temp2 ; clk        ; clk      ; None                        ; None                      ; 0.768 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[1]   ; cnt2[0]   ; clk        ; clk      ; None                        ; None                      ; 0.766 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[1]   ; cnt2[2]   ; clk        ; clk      ; None                        ; None                      ; 0.765 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[0]   ; cnt1[1]   ; clk        ; clk      ; None                        ; None                      ; 0.764 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[0]   ; clk_temp1 ; clk        ; clk      ; None                        ; None                      ; 0.761 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[0]   ; cnt1[2]   ; clk        ; clk      ; None                        ; None                      ; 0.761 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[0]   ; cnt2[1]   ; clk        ; clk      ; None                        ; None                      ; 0.760 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; clk_temp2 ; clk_temp2 ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[2]   ; cnt2[2]   ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[0]   ; cnt2[0]   ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt2[1]   ; cnt2[1]   ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; clk_temp1 ; clk_temp1 ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[1]   ; cnt1[1]   ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[2]   ; cnt1[2]   ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt1[0]   ; cnt1[0]   ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
+-------+------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 8.846 ns   ; clk_temp2 ; div5 ; clk        ;
; N/A   ; None         ; 7.780 ns   ; clk_temp1 ; div5 ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition
    Info: Processing started: Mon Nov 17 11:48:08 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div5 -c div5 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "cnt1[1]" and destination register "clk_temp1"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.536 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X7_Y1_N9; Fanout = 4; REG Node = 'cnt1[1]'
            Info: 2: + IC(0.778 ns) + CELL(0.650 ns) = 1.428 ns; Loc. = LCCOMB_X7_Y1_N18; Fanout = 1; COMB Node = 'clk_temp1~68'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.536 ns; Loc. = LCFF_X7_Y1_N19; Fanout = 2; REG Node = 'clk_temp1'
            Info: Total cell delay = 0.758 ns ( 49.35 % )
            Info: Total interconnect delay = 0.778 ns ( 50.65 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.751 ns
                Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.842 ns) + CELL(0.666 ns) = 2.751 ns; Loc. = LCFF_X7_Y1_N19; Fanout = 2; REG Node = 'clk_temp1'
                Info: Total cell delay = 1.766 ns ( 64.19 % )
                Info: Total interconnect delay = 0.985 ns ( 35.81 % )
            Info: - Longest clock path from clock "clk" to source register is 2.751 ns
                Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.842 ns) + CELL(0.666 ns) = 2.751 ns; Loc. = LCFF_X7_Y1_N9; Fanout = 4; REG Node = 'cnt1[1]'
                Info: Total cell delay = 1.766 ns ( 64.19 % )
                Info: Total interconnect delay = 0.985 ns ( 35.81 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "clk" to destination pin "div5" through register "clk_temp2" is 8.846 ns
    Info: + Longest clock path from clock "clk" to source register is 2.751 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.842 ns) + CELL(0.666 ns) = 2.751 ns; Loc. = LCFF_X7_Y1_N25; Fanout = 2; REG Node = 'clk_temp2'
        Info: Total cell delay = 1.766 ns ( 64.19 % )
        Info: Total interconnect delay = 0.985 ns ( 35.81 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.791 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X7_Y1_N25; Fanout = 2; REG Node = 'clk_temp2'
        Info: 2: + IC(1.090 ns) + CELL(0.624 ns) = 1.714 ns; Loc. = LCCOMB_X7_Y1_N12; Fanout = 1; COMB Node = 'div5~0'
        Info: 3: + IC(0.841 ns) + CELL(3.236 ns) = 5.791 ns; Loc. = PIN_51; Fanout = 0; PIN Node = 'div5'
        Info: Total cell delay = 3.860 ns ( 66.66 % )
        Info: Total interconnect delay = 1.931 ns ( 33.34 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 123 megabytes
    Info: Processing ended: Mon Nov 17 11:48:09 2008
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01