adder1.fit.summary

一个全加器的VHDL程序,经过编译和仿真.

Fitter Status : Successful - Wed Oct 29 22:08:13 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : adder1
Top-level Entity Name : adder1
Family : Cyclone
Device : EP1C6Q240C6
Timing Models : Final
Total logic elements : 2 / 5,980 ( < 1 % )
Total pins : 5 / 185 ( 3 % )
Total virtual pins : 0
Total memory bits : 0 / 92,160 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )