adder1.vhd

来自「一个全加器的VHDL程序,经过编译和仿真.」· VHDL 代码 · 共 21 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY adder1 IS 
  PORT(a,b,cin:IN STD_LOGIC;
       sum,cout:OUT STD_LOGIC);
END adder1;
ARCHITECTURE m OF adder1 IS
   SIGNAL tmp1,tmp2,tmp3,tmp4,tmp5:STD_LOGIC;
     BEGIN
         PROCESS(a,b,cin,tmp1,tmp2,tmp3,tmp4,tmp5)
           BEGIN
             tmp1<=a XOR b;
             tmp2<=a NAND b;
             tmp3<=cin NAND tmp1;
             tmp4<=tmp1 XOR cin;
             tmp5<=tmp2 NAND tmp3;
          END PROCESS;
       sum<=tmp4;
       cout<=tmp5;
 END m;