sign.v

来自「Log Shifter Gate Level Design using Veri」· Verilog 代码 · 共 47 行

//############################################################################
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//   (C) Copyright Laboratory System Integration and Silicon Implementation
//   All Right Reserved
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//   2004 ICLAB(I) Course
//   Lab01      : Structural Arithmetic Design
//   Exercise_1 : 16-bits barrel shifter gate-level design
//   Author     : Chih-Lung Chen ([e-mail])
//
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//   File Name   : SIGN.v
//   Module Name : SIGN
//   Release version : V1.0 (Release Date: 7-20-2004)
//
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// PURPOSE: Generate sign extension bit for shift right operation of
//          signed data.
//############################################################################

module SIGN
(
  // Output Port
  EXTEND,

  // Input Port
  SIGN, IN_MSB
);

//---------------------------------------------------------------------
// INPUT AND OUTPUT DECLARATION
//---------------------------------------------------------------------

output EXTEND;  // for sign extension
input  SIGN;    // decide sign or unsign
input  IN_MSB;  // MSB of input data

//---------------------------------------------------------------------
// GATE LEVEL DESCRIPTION OF COMBINATIONAL LOGIC
//---------------------------------------------------------------------

and #( 0.9:0.6:0.4 , 0.8:0.6:0.4 ) ( EXTEND, SIGN, IN_MSB );

endmodule