_primary.vhd

来自「Log Shifter Gate Level Design using Veri」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity pattern is
    generic(
        seednum          : integer := 10
    );
    port(
        \IN\            : out    vl_logic_vector(15 downto 0);
        shift           : out    vl_logic_vector(3 downto 0);
        right           : out    vl_logic;
        sign            : out    vl_logic;
        \OUT\           : in     vl_logic_vector(15 downto 0)
    );
end pattern;