_primary.vhd

来自「Log Shifter Gate Level Design using Veri」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity sign is
    port(
        extend          : out    vl_logic;
        sign            : in     vl_logic;
        in_msb          : in     vl_logic
    );
end sign;