_primary.vhd

来自「Log Shifter Gate Level Design using Veri」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity mux16_stage1 is
    port(
        mux_out         : out    vl_logic_vector(15 downto 0);
        \IN\            : in     vl_logic_vector(15 downto 0);
        in_r            : in     vl_logic_vector(15 downto 0);
        in_l            : in     vl_logic_vector(15 downto 0);
        right           : in     vl_logic;
        ctrl            : in     vl_logic;
        sign            : in     vl_logic
    );
end mux16_stage1;