_info

Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note

m255
o
cModel Technology
dD:\alan\IC LAB\alan\book\ex7_6_1_whileLoop
vMUX16
IAiKoKTef=h_OO0OW7ij5d3
Vljj?VJd6N?ioCHHgBVSlk3
dD:\alan\IC LAB\alan\IC LAB\lab01\Demo\LAB01_EX1_ANS
w1190292525
FD:/alan/IC LAB/alan/IC LAB/lab01/Demo/LAB01_EX1_ANS/SHIFTER.v
FMUX16.v
L1 21
OE;L;5.5e;17
r1
31
o-work work
n@m@u@x16
vMUX16_STAGE1
I0QM]hb_B3EhY?jIGFL;Ek2
V:C[c4l?e;VQ5J89d5SOOC1
dD:\alan\IC LAB\alan\IC LAB\lab01\Demo\LAB01_EX1_ANS
w1074009600
FMUX16_STAGE1.v
L0 25
OE;L;5.5e;17
r1
31
o-work work
n@m@u@x16_@s@t@a@g@e1
vPATTERN
IPfNSi@f7]ED0HnndGYAXO1
V^j?cQdDdHHE[K8?bR]CzX0
dD:\alan\IC LAB\alan\IC LAB\lab01\Demo\LAB01_EX1_ANS
w1092652850
FD:/alan/IC LAB/alan/IC LAB/lab01/Demo/LAB01_EX1_ANS/PATTERN.v
L0 21
OE;L;5.5e;17
r1
31
o-work work
n@p@a@t@t@e@r@n
vSHIFTER
I7Y3[9dG=YEZGHUQ>_ai8_2
Vd7ok=HPKUGFm=nj`KY`;h1
dD:\alan\IC LAB\alan\IC LAB\lab01\Demo\LAB01_EX1_ANS
w1190292525
FD:/alan/IC LAB/alan/IC LAB/lab01/Demo/LAB01_EX1_ANS/SHIFTER.v
L0 24
OE;L;5.5e;17
r1
31
o-work work
n@s@h@i@f@t@e@r
vSIGN
Ila`L2>4[6>GIed0lA1Dh83
Vm8eYmJ^z_PVET2_o4h7:`1
dD:\alan\IC LAB\alan\IC LAB\lab01\Demo\LAB01_EX1_ANS
w1074009600
FD:/alan/IC LAB/alan/IC LAB/lab01/Demo/LAB01_EX1_ANS/SIGN.v
L0 23
OE;L;5.5e;17
r1
31
o-work work
n@s@i@g@n
vTESTBED
ILCOG8fe9S5zY<3NR]@8O03
VD6`0km<]9mJmS`2X:P3YL1
dD:\alan\IC LAB\alan\IC LAB\lab01\Demo\LAB01_EX1_ANS
w1092652870
FD:/alan/IC LAB/alan/IC LAB/lab01/Demo/LAB01_EX1_ANS/TESTBED.v
L0 26
OE;L;5.5e;17
r1
31
o-work work
n@t@e@s@t@b@e@d