_primary.vhd

Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note

library verilog;
use verilog.vl_types.all;
entity pattern is
    generic(
        max_cycle        : real    := 50.000000
    );
    port(
        out0            : in     vl_logic_vector(10 downto 0);
        out1            : in     vl_logic_vector(10 downto 0);
        out2            : in     vl_logic_vector(10 downto 0);
        out3            : in     vl_logic_vector(10 downto 0);
        a               : out    vl_logic_vector(7 downto 0);
        b               : out    vl_logic_vector(7 downto 0);
        c               : out    vl_logic_vector(7 downto 0);
        d               : out    vl_logic_vector(7 downto 0);
        mode            : out    vl_logic_vector(1 downto 0)
    );
end pattern;