_primary.vhd

Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note

library verilog;
use verilog.vl_types.all;
entity partial_sum is
    port(
        partial_out     : out    vl_logic_vector(10 downto 0);
        a               : in     vl_logic_vector(7 downto 0);
        b               : in     vl_logic_vector(7 downto 0);
        c               : in     vl_logic_vector(7 downto 0);
        d               : in     vl_logic_vector(7 downto 0);
        c1              : in     vl_logic_vector(2 downto 0);
        c2              : in     vl_logic_vector(2 downto 0);
        c3              : in     vl_logic_vector(2 downto 0);
        c4              : in     vl_logic_vector(2 downto 0)
    );
end partial_sum;