_primary.vhd

来自「Log Shifter Gate Level Design using Veri」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity mux4_to_1 is
    port(
        \out\           : out    vl_logic;
        i0              : in     vl_logic;
        i1              : in     vl_logic;
        i2              : in     vl_logic;
        i3              : in     vl_logic;
        s1              : in     vl_logic;
        s0              : in     vl_logic
    );
end mux4_to_1;