_info

Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note

m255
o
cModel Technology
dD:\alan\IC LAB\alan\IC LAB\lab01\Demo\LAB01_EX1_ANS
vfulladd
I:@z]k7?G`Pi_QWdPMCW`?1
V@V_f]oGec?Xz_H4zH_A:J3
dD:\alan\IC LAB\alan\IC LAB\lab01\ex1
w1190652956
Ffulladd.v
L0 2
OE;L;5.5e;17
r1
31
o-work work
vfulladd4
I[9oe<BJRK??3^mVPP>LZP3
V=Wg9]B[_b_D_SW^HiVQ`A1
dD:\alan\IC LAB\alan\IC LAB\lab01\ex1
w1190641413
Ffulladd4.v
L0 1
OE;L;5.5e;17
r1
31
o-work work
vmux2_to_1
IVm0c2>fCm?Vl?3@W[E4_M1
V@cXL<NDa2TZSKES]j2H[Q3
dD:\alan\IC LAB\alan\IC LAB\lab01\ex1
w1190734830
Fmux2_to_1.v
L0 1
OE;L;5.5e;17
r1
31
o-work work
vmux4_to_1
I6NjGY9Mf[W1nX4HKV_8KM1
V8Yo=3J>CGW_oQIMGjhH1:0
dD:\alan\IC LAB\alan\IC LAB\lab01\ex1
w1190781234
FD:/alan/IC LAB/alan/IC LAB/lab01/ex1/mux4_to_1.v
L0 1
OE;L;5.5e;17
r1
31
o-work work
vpartial_sum
I@BkZdeno5j=XeOC?X5C`?3
Vl2n`:`Zo3Cg_MU?mlTz721
dD:\alan\IC LAB\alan\IC LAB\lab01\ex1
w1190815304
FD:/alan/IC LAB/alan/IC LAB/lab01/ex1/partial_sum.v
L0 1
OE;L;5.5e;17
r1
31
o-work work
vPATTERN
I8[_mSXfADHEWdQL0=LcdM3
VnQ8TKABWhJJo2cGoHiZHf3
dD:\alan\IC LAB\alan\IC LAB\lab01\ex1
w1190691383
FD:/alan/IC LAB/alan/IC LAB/lab01/ex1/PATTERN.v
L0 2
OE;L;5.5e;17
r1
31
o-work work
n@p@a@t@t@e@r@n
vposneg_conveter
IKL_Xa4]5be6;FZ<9B39nE0
V05Im2ZjokfK89Mj1V_6_]0
dD:\alan\IC LAB\alan\IC LAB\lab01\ex1
w1190805995
Fposneg_conveter.v
L0 1
OE;L;5.5e;17
r1
31
o-work work
vspec_multiply
ITizlL]hQAm6^izJ4Vci2z2
ViK[bjR2jLSYX8@G=7P@7K1
dD:\alan\IC LAB\alan\IC LAB\lab01\ex1
w1190815299
Fspec_multiply.v
L0 1
OE;L;5.5e;17
r1
31
o-work work
vTESTBED
Im<_=LB3`BRF`Xf41^Xlf11
VD6`0km<]9mJmS`2X:P3YL1
dD:\alan\IC LAB\alan\IC LAB\lab01\ex1
w1190691467
FD:/alan/IC LAB/alan/IC LAB/lab01/ex1/TESTBED.v
L0 5
OE;L;5.5e;17
r1
31
o-work work
n@t@e@s@t@b@e@d
vTRANS
In4?2XSFnEIbPk1jTRB7H^3
VA7RX8FW8J9LG=7jIE^82F0
dD:\alan\IC LAB\alan\IC LAB\lab01\ex1
w1190814564
FD:/alan/IC LAB/alan/IC LAB/lab01/ex1/TRANS.v
L0 11
OE;L;5.5e;17
r1
31
o-work work
n@t@r@a@n@s