_primary.vhd

来自「Log Shifter Gate Level Design using Veri」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity spec_multiply is
    port(
        \out\           : out    vl_logic_vector(8 downto 0);
        \in\            : in     vl_logic_vector(7 downto 0);
        \select\        : in     vl_logic_vector(1 downto 0)
    );
end spec_multiply;