freedev_cycloneii_50.fit.qmsg

verilog 代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Aug 11 17:53:34 2006 " "Info: Processing started: Fri Aug 11 17:53:34 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off freedev_cycloneII_50 -c freedev_cycloneII_50 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off freedev_cycloneII_50 -c freedev_cycloneII_50" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "freedev_cycloneII_50 EP2C35F484C8 " "Info: Selected device EP2C35F484C8 for design \"freedev_cycloneII_50\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C20F484C8 " "Info: Device EP2C20F484C8 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C8 " "Info: Device EP2C50F484C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "1 56 " "Info: No exact pin location assignment(s) for 1 pins of 56 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "A\[0\] " "Info: Pin A\[0\] not assigned to an exact location on the device" {  } { { "freedev_cycloneII_50_top.bdf" "" { Schematic "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50_top.bdf" { { 128 952 1128 144 "A\[24..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "A\[0\]" } } } } { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { A[0] } "NODE_NAME" } "" } } { "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" { Floorplan "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" "" { A[0] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK (placed in PIN M22 (CLK6, LVDSCLK3p, Input)) " "Info: Automatically promoted node CLK (placed in PIN M22 (CLK6, LVDSCLK3p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G7 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7" {  } {  } 0}  } { { "freedev_cycloneII_50_top.bdf" "" { Schematic "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50_top.bdf" { { 104 232 400 120 "CLK" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" "" { Report "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50_cmp.qrpt" Compiler "freedev_cycloneII_50" "UNKNOWN" "V1" "J:/board/freedev_cycloneII_50/system/db/freedev_cycloneII_50.quartus_db" { Floorplan "J:/board/freedev_cycloneII_50/system/" "" "" { CLK } "NODE_NAME" } "" } } { "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" { Floorplan "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.fld" "" "" { CLK } "NODE_NAME" } }  } 0}