vhdl.txt

来自「半加器 或门 1位二进制全加器顶层设计描述」· 文本 代码 · 共 66 行

半加器
[3-15]------------(1)半加器描述:布尔方程描述法
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY h_adder IS
  PORT (a,b: IN STD_LOGIC;
        co,so: OUT STD_LOGIC);
END ENTITY h_adder;
ARCHITECTURE fh1 OF h_adder is
BEGIN
 so<=NOT(a XOR (NOT b)); co<=a AND b;
END ARCHITECTURE fh1;
[3-16]-----------------(2)半加器描述:真值表描述法
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY h_adder IS
PORT(a,b: IN STD_LOGIC;
     co,so:OUT STD_LOGIC);
END ENTITY h_adder IS
ARCHITECTURE fh1 OF h_adder is
 SIGNAL abc:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
abc<=a&b;
PROCESS(abc)
BEGIN
 CASE abc IS
  WHEN "00"=>so<='0';co<='0';
  WHEN "01"=>so<='1';co<='0';
  WHEN "10"=>so<='1';co<='0';
  WHEN "11"=>so<='0';co<='1';
  WHEN OTHERS=>NULL;
END CASE;
 END PROCESS;
END ARCHITECTURE fh1;	
[3-17]-----------------或门逻辑描述
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY or2a IS
  PORT(a,b:IN STD_LOGIC; c:OUT STD_LOGIC);
END ENTITY or2a;
ARCHITECTURE one OF or3a IS
  BEGIN
  c<=a OR b;
END ARCHITECTURE one;
[3-18]--------------------1位二进制全加器顶层设计描述
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
 ENTITY f_adder IS
   PORT(ain,bin,cin:IN STD_LOGIC;
           cout,sum:OUT STD_LOGIC);
END ENTITY f_adder;
ARCHITECTURE fd1 OF f_adder IS
  COMPONENT h_adder
    PORT(a,b:IN STD_LOGIC;
       co,so:OUT STD_LOGIC);
  END COMPONENT;
  CCOMPONENT or2a
    PORT(a,b:IN STD_LOGIC;
           c:OUT STD_LOGIC);
  END COMPONENT;
SIGNAL d,e,f: STD_LOGIC;
 BEGIN
  u1: h_adder PORT MAP(a=>ain,b=>bin,co=>d,so=>e);
  u2: h_adder PORT MAP(a=>e,b=>cin,co=>f,so=>sum);
  u3:   or2a PORT MAP(a=>d,b=>f,c=>cout);
 END ARCHITECTURE fd1;