check.v

本程序是在传输流传输过程中对节目时钟字段进行检测与修改,采用Verilog HDL 语言进行编程。

module check(data_in,clk,data_out,counterflag);
input clk;
input [7:0] data_in;
output [7:0] data_out;
//output counter2;
output counterflag;
reg counterflag;
reg [7:0] data_out;
reg [7:0] buffer;
reg [7:0] counter2;
reg flag0;
reg flag;

initial
begin
counter2=0;
flag0=0;
end

always@(posedge clk)
begin
buffer=data_in;
if (buffer==8'h47 & flag0==0)
	begin
	counter2=0;
	flag0=1;
	end
if (flag0==1)
	counter2=counter2+1;
if (counter2==188+1)
	begin
	if (buffer==8'h47)
		begin
		counter2=0;
		flag=1;
		counterflag=1;
		end
end
if (flag==1)
data_out=buffer;
end
endmodule