ts_generator.v

来自「本程序是在传输流传输过程中对节目时钟字段进行检测与修改,采用Verilog HD」· Verilog 代码 · 共 33 行

module ts_generator (ts,clk,counter);
input  clk;
output [7:0] ts;
output [7:0] counter;
//output[7:0] counter;
reg	   [7:0] ts;
reg		[7:0]	counter;	

initial
counter<=0;






always@(posedge clk)
begin
counter=counter+1;
if(counter==188)
counter=0;
end



always@(posedge clk)
if (counter==0)
ts=8'h47;
else 
ts=8'hFF;
endmodule