clock_pr.v

本程序是在传输流传输过程中对节目时钟字段进行检测与修改,采用Verilog HDL 语言进行编程。

//clock  module
module clock_pr(clk_in,reset,clk_o2,clk_o3);
input clk_in;
input reset;
output clk_o2;//27/8
output clk_o3;//90


reg clk_o2;
reg clk_o3;

reg [3:0] counter0;
reg [9:0] counter1;


always@(posedge clk_in)
begin
  if(reset==0) 
          begin
               counter0=0;
               counter1=0;
          end
  else
   begin

       if(counter0<8)  counter0=counter0+1;
       if (counter0==8)  counter0=0;
    	if(counter0<4)  clk_o2<=1'b0;
    	else 
         	clk_o2<=1'b1;
    
    if(counter1<300)   counter1=counter1+1;
    if (counter1==300)  counter1=0;
        if(counter1<150)
        	 clk_o3<=1'b0;
    	else 
         	clk_o3<=1'b1;
    	
   end

end
endmodule