top.v

本程序是在传输流传输过程中对节目时钟字段进行检测与修改,采用Verilog HDL 语言进行编程。

`include  "clock_pr.v"
`include  "counter.v"
`include  "correction.v"
`include "check.v"
`include "ts_generator.v"
`include "delay.v"
`include "correction_out.v"
module top(reset,clk,data_out,data_out10,data_out11);
output [7:0] data_out;
output [7:0] data_out10,data_out11;

//input [7:0] data_in;
input reset,clk;

wire clko3,clko2,flag2,flag3;
wire [7:0] data_out0,data_out1,data_out3,data_out4,data_out5,counter0;
wire  [7:0] data_out2;
wire [16:0] pcr_33_1;
wire [15:0] pcr_33_2;
wire [8:0]  pcr_9;

reg [7:0] data_out;
reg [7:0] data_out10,data_out11;



clock_pr clock_pr0(.clk_in(clk),
         .reset(reset),
         .clk_o2(clko2),
         .clk_o3(clko3)
         );
ts_generator ts0(.clk(clko2),
       .ts(data_out0),
       .counter(counter0)
        );

counter counter1(.clk_27(clk),
        .clk_90(clko3),
        .pcr_33_1(pcr_33_1),
		.pcr_33_2(pcr_33_2),
		.pcr_9(pcr_9)
        );
correction correction0(.clk(clko2),
          .flag(flag2),
          .pcr_33_1(pcr_33_1),
		  .pcr_33_2(pcr_33_2),
		  .pcr_9(pcr_9),
          .counter(counter0),
          .data_in(data_out1),
          .data_out(data_out2)
          );

check check0(.data_in(data_out0),
         .clk(clko2),
         .data_out(data_out1),
         .counterflag(flag2)
         );
delay delay0(.clk(clko2),
			.data_in(data_out2),
			.data_out(data_out3)
			);
check check1(.data_in(data_out3),
         .clk(clko2),
         .data_out(data_out4),
         .counterflag(flag3)
         );
correction_out correction1(.clk(clko2),
          .flag(flag3),
          .pcr_33_1(pcr_33_1),
		  .pcr_33_2(pcr_33_2),
		  .pcr_9(pcr_9),
          .data_in(data_out4),
          .data_out(data_out5)
          );

always @(posedge clk)
begin
           
          data_out<=data_out5;
          data_out10<=data_out1;
		  data_out11<=data_out2;
end
endmodule