delay.v

来自「本程序是在传输流传输过程中对节目时钟字段进行检测与修改,采用Verilog HD」· Verilog 代码 · 共 21 行

module delay(clk,data_in,data_out);
input clk;
input [7:0] data_in;
output [7:0] data_out;

reg [7:0] data_out,buffer0,buffer1,buffer2,buffer3,buffer4;

always@(posedge clk)
begin
buffer0<=data_in;
buffer1<=buffer0;
buffer2<=buffer1;
buffer3<=buffer2;
buffer4<=buffer3;
data_out<=buffer4;
end

endmodule