correction_out.v

本程序是在传输流传输过程中对节目时钟字段进行检测与修改,采用Verilog HDL 语言进行编程。

//校正算法
module correction_out(clk,flag,pcr_33_1,pcr_33_2,pcr_9,data_in,data_out);
output[7:0] data_out;
input clk;
input flag;
input [7:0] data_in;

input [16:0] pcr_33_1;//低位
input [15:0] pcr_33_2;//高位
input [8:0]  pcr_9;


reg [7:0]buffer0,buffer1,buffer2,buffer3,buffer4,buffer5,buffer6,buffer7;
reg [7:0] counter;
reg[0:0] adaflag;//自适应标志
reg[0:0] pcrflag;//pcr标志
reg[7:0] data_out;



always@(posedge clk)
begin
   buffer0<=data_in;
   buffer1<=buffer0;
   buffer2<=buffer1; 
   buffer3<=buffer2;
   buffer4<=buffer3;
   buffer5<=buffer4;
   buffer6<=buffer5;
   buffer7<=buffer6;
   data_out<=buffer7;
if(flag==1)
begin  
   if(counter<187)   counter<=counter+1;
   if(counter==187)  counter<=0;
   if(counter==4)
      begin  
       if(data_in[5]==1)  adaflag<=1'b1;
      end
   if(adaflag==1&pcrflag==0)
       begin 
          if(counter==6)
               begin
                if(data_in[4]==1) pcrflag<=1'b1;
               end
       end
   if(pcrflag==1)
        begin
          if(counter==13)
             begin
                 if(buffer0+pcr_9[7:0]>8'hff)  buffer1<=buffer1+1;
				 if(buffer1[7]==1&pcr_9[8]==1)  buffer2<=buffer2+1;
                 if(buffer2+pcr_33_1[9:1]>8'hff)  buffer3<=buffer3+1;
				 if(buffer3+pcr_33_1[16:9]>8'hff)  buffer4<=buffer4+1;
                 if(buffer4+pcr_33_2[7:0]>8'hff)  buffer5<=buffer5+1;
                 
                 buffer5<=buffer5+pcr_33_2[15:8];
                 buffer4<=buffer4+pcr_33_2[7:0];
                 buffer3<=buffer3+pcr_33_1[16:9];
                 buffer2<=buffer2+pcr_33_1[9:1];
                 buffer0<=buffer0+pcr_9[7:0];
                 if(pcr_9[8]==1&pcr_33_1[0]==1)  buffer0<=buffer0+8'b10000001;
                 if(pcr_9[8]==1&pcr_33_1[0]==0)  buffer0<=buffer0+8'b00000001;
                 if(pcr_9[8]==0&pcr_33_1[0]==1)  buffer0<=buffer0+8'b10000000;
              
             end
         end

   if(counter==14)
         begin
             pcrflag<=1'b0;
             adaflag<=1'b0;
         end                        
end
end
endmodule