pcr.v

本程序是在传输流传输过程中对节目时钟字段进行检测与修改,采用Verilog HDL 语言进行编程。

module pcr(data_out,flag2,clk,data_in);
output[7:0]  data_out;
output flag2;//同步和计数器启动标志,flag2包头标志
input clk;
input [7:0] data_in;

reg [7:0] buffer0;
reg [7:0] data_out;
integer counter0;
integer counter1;
reg flag0;
reg flag1,flag2;
reg flag,counterflag;


always@(posedge clk)
begin
   buffer0[7:0]<=data_in[7:0];
   if(buffer0[7:0]==8'b01000111)    
         begin
               flag0=1;//counter=0; 
         end
   if(flag0==1)    counter0=counter0+1;
   if(counter0==188)  
        begin
           if(buffer0[7:0]==8'b01000111)   
                  begin
                        flag1=1;
                        counter0=0;
                        counter1=0;
                  end
            else 
                  begin
                         counter0=0;
                         flag0=0;
                         flag1=0;
                   end
        end 
    if(flag1==1)  
        begin 
           data_out[7:0]=buffer0[7:0];
            flag =flag1;
            counterflag=flag1;
            if(counter0==0)  	flag2=1'b1;
             else  flag2=1'b0;

        end
  end

endmodule