lab7.map.rpt

用VHDL编译的源代码

+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 76    ;
;                                             ;       ;
; Total combinational functions               ; 76    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 18    ;
;     -- 3 input functions                    ; 5     ;
;     -- <=2 input functions                  ; 53    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 39    ;
;     -- arithmetic mode                      ; 37    ;
;                                             ;       ;
; Total registers                             ; 36    ;
;     -- Dedicated logic registers            ; 36    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 29    ;
; Maximum fan-out node                        ; clk1  ;
; Maximum fan-out                             ; 36    ;
; Total fan-out                               ; 272   ;
; Average fan-out                             ; 1.93  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |lab7                      ; 76 (0)            ; 36 (0)       ; 0           ; 0            ; 0       ; 0         ; 29   ; 0            ; |lab7               ; work         ;
;    |bin2led0:u2|           ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab7|bin2led0:u2   ; work         ;
;    |bin2led1:u3|           ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab7|bin2led1:u3   ; work         ;
;    |bin2led2:u4|           ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab7|bin2led2:u4   ; work         ;
;    |bin2led3:u5|           ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab7|bin2led3:u5   ; work         ;
;    |heartbeat:u1|          ; 70 (70)           ; 36 (36)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab7|heartbeat:u1  ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------+
; Registers Removed During Synthesis                                         ;
+---------------------------------------+------------------------------------+
; Register name                         ; Reason for Removal                 ;
+---------------------------------------+------------------------------------+
; heartbeat:u1|d3_reg[0]                ; Merged with heartbeat:u1|d0_reg[0] ;
; heartbeat:u1|d1_reg[0]                ; Merged with heartbeat:u1|d0_reg[0] ;
; heartbeat:u1|d2_reg[0]                ; Merged with heartbeat:u1|d0_reg[0] ;
; heartbeat:u1|d2_reg[1]                ; Merged with heartbeat:u1|d0_reg[1] ;
; heartbeat:u1|d3_reg[1]                ; Merged with heartbeat:u1|d0_reg[1] ;
; heartbeat:u1|d1_reg[1]                ; Merged with heartbeat:u1|d0_reg[1] ;
; Total Number of Removed Registers = 6 ;                                    ;
+---------------------------------------+------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 36    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Web Edition
    Info: Processing started: Wed Oct 29 16:35:57 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lab7 -c lab7
Info: Found 2 design units, including 1 entities, in source file lab7.vhd
    Info: Found design unit 1: lab7-one
    Info: Found entity 1: lab7
Info: Elaborating entity "lab7" for the top level hierarchy
Warning: Using design file heartbeat.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: heartbeat-one
    Info: Found entity 1: heartbeat
Info: Elaborating entity "heartbeat" for hierarchy "heartbeat:u1"
Warning: Using design file bin2led0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: bin2led0-arch
    Info: Found entity 1: bin2led0
Info: Elaborating entity "bin2led0" for hierarchy "bin2led0:u2"
Warning: Using design file bin2led1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: bin2led1-arch
    Info: Found entity 1: bin2led1
Info: Elaborating entity "bin2led1" for hierarchy "bin2led1:u3"
Warning: Using design file bin2led2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: bin2led2-arch
    Info: Found entity 1: bin2led2
Info: Elaborating entity "bin2led2" for hierarchy "bin2led2:u4"
Warning: Using design file bin2led3.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: bin2led3-arch
    Info: Found entity 1: bin2led3
Info: Elaborating entity "bin2led3" for hierarchy "bin2led3:u5"
Info: Duplicate registers merged to single register
    Info (13350): Duplicate register "heartbeat:u1|d3_reg[0]" merged to single register "heartbeat:u1|d0_reg[0]"
    Info (13350): Duplicate register "heartbeat:u1|d1_reg[0]" merged to single register "heartbeat:u1|d0_reg[0]"
    Info (13350): Duplicate register "heartbeat:u1|d2_reg[0]" merged to single register "heartbeat:u1|d0_reg[0]"
    Info (13350): Duplicate register "heartbeat:u1|d2_reg[1]" merged to single register "heartbeat:u1|d0_reg[1]"
    Info (13350): Duplicate register "heartbeat:u1|d3_reg[1]" merged to single register "heartbeat:u1|d0_reg[1]"
    Info (13350): Duplicate register "heartbeat:u1|d1_reg[1]" merged to single register "heartbeat:u1|d0_reg[1]"
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "ssega[0]" is stuck at VCC
    Warning (13410): Pin "ssega[3]" is stuck at VCC
    Warning (13410): Pin "ssega[4]" is stuck at VCC
    Warning (13410): Pin "ssega[5]" is stuck at VCC
    Warning (13410): Pin "ssega[6]" is stuck at VCC
    Warning (13410): Pin "ssegb[0]" is stuck at VCC
    Warning (13410): Pin "ssegb[3]" is stuck at VCC
    Warning (13410): Pin "ssegb[6]" is stuck at VCC
    Warning (13410): Pin "ssegc[0]" is stuck at VCC
    Warning (13410): Pin "ssegc[3]" is stuck at VCC
    Warning (13410): Pin "ssegc[6]" is stuck at VCC
    Warning (13410): Pin "ssegd[0]" is stuck at VCC
    Warning (13410): Pin "ssegd[1]" is stuck at VCC
    Warning (13410): Pin "ssegd[2]" is stuck at VCC
    Warning (13410): Pin "ssegd[3]" is stuck at VCC
    Warning (13410): Pin "ssegd[6]" is stuck at VCC
Info: Implemented 105 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 28 output pins
    Info: Implemented 76 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 22 warnings
    Info: Peak virtual memory: 180 megabytes
    Info: Processing ended: Wed Oct 29 16:36:06 2008
    Info: Elapsed time: 00:00:09
    Info: Total CPU time (on all processors): 00:00:04