prev_cmp_lab7.fit.qmsg

用VHDL编译的源代码

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.503 ns register register " "Info: Estimated most critical path is register to register delay of 5.503 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns heartbeat:u1\|ms_reg\[23\] 1 REG LAB_X30_Y23 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X30_Y23; Fanout = 3; REG Node = 'heartbeat:u1\|ms_reg\[23\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { heartbeat:u1|ms_reg[23] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.135 ns) + CELL(0.177 ns) 1.312 ns heartbeat:u1\|Equal0~292 2 COMB LAB_X29_Y24 1 " "Info: 2: + IC(1.135 ns) + CELL(0.177 ns) = 1.312 ns; Loc. = LAB_X29_Y24; Fanout = 1; COMB Node = 'heartbeat:u1\|Equal0~292'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.312 ns" { heartbeat:u1|ms_reg[23] heartbeat:u1|Equal0~292 } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.154 ns) + CELL(0.521 ns) 1.987 ns heartbeat:u1\|Equal0~293 3 COMB LAB_X29_Y24 1 " "Info: 3: + IC(0.154 ns) + CELL(0.521 ns) = 1.987 ns; Loc. = LAB_X29_Y24; Fanout = 1; COMB Node = 'heartbeat:u1\|Equal0~293'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.675 ns" { heartbeat:u1|Equal0~292 heartbeat:u1|Equal0~293 } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.178 ns) 2.663 ns heartbeat:u1\|Equal0~294 4 COMB LAB_X29_Y24 20 " "Info: 4: + IC(0.498 ns) + CELL(0.178 ns) = 2.663 ns; Loc. = LAB_X29_Y24; Fanout = 20; COMB Node = 'heartbeat:u1\|Equal0~294'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { heartbeat:u1|Equal0~293 heartbeat:u1|Equal0~294 } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.013 ns) + CELL(0.517 ns) 4.193 ns heartbeat:u1\|Add3~49 5 COMB LAB_X27_Y24 1 " "Info: 5: + IC(1.013 ns) + CELL(0.517 ns) = 4.193 ns; Loc. = LAB_X27_Y24; Fanout = 1; COMB Node = 'heartbeat:u1\|Add3~49'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.530 ns" { heartbeat:u1|Equal0~294 heartbeat:u1|Add3~49 } "NODE_NAME" } } { "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" "" { Text "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" 1244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.273 ns heartbeat:u1\|Add3~51 6 COMB LAB_X27_Y24 2 " "Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 4.273 ns; Loc. = LAB_X27_Y24; Fanout = 2; COMB Node = 'heartbeat:u1\|Add3~51'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { heartbeat:u1|Add3~49 heartbeat:u1|Add3~51 } "NODE_NAME" } } { "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" "" { Text "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" 1244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 4.731 ns heartbeat:u1\|Add3~52 7 COMB LAB_X27_Y24 1 " "Info: 7: + IC(0.000 ns) + CELL(0.458 ns) = 4.731 ns; Loc. = LAB_X27_Y24; Fanout = 1; COMB Node = 'heartbeat:u1\|Add3~52'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { heartbeat:u1|Add3~51 heartbeat:u1|Add3~52 } "NODE_NAME" } } { "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" "" { Text "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" 1244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.131 ns) + CELL(0.545 ns) 5.407 ns heartbeat:u1\|d2_next\[2\]~41 8 COMB LAB_X27_Y24 1 " "Info: 8: + IC(0.131 ns) + CELL(0.545 ns) = 5.407 ns; Loc. = LAB_X27_Y24; Fanout = 1; COMB Node = 'heartbeat:u1\|d2_next\[2\]~41'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { heartbeat:u1|Add3~52 heartbeat:u1|d2_next[2]~41 } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 5.503 ns heartbeat:u1\|d2_reg\[2\] 9 REG LAB_X27_Y24 5 " "Info: 9: + IC(0.000 ns) + CELL(0.096 ns) = 5.503 ns; Loc. = LAB_X27_Y24; Fanout = 5; REG Node = 'heartbeat:u1\|d2_reg\[2\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { heartbeat:u1|d2_next[2]~41 heartbeat:u1|d2_reg[2] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.572 ns ( 46.74 % ) " "Info: Total cell delay = 2.572 ns ( 46.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.931 ns ( 53.26 % ) " "Info: Total interconnect delay = 2.931 ns ( 53.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "5.503 ns" { heartbeat:u1|ms_reg[23] heartbeat:u1|Equal0~292 heartbeat:u1|Equal0~293 heartbeat:u1|Equal0~294 heartbeat:u1|Add3~49 heartbeat:u1|Add3~51 heartbeat:u1|Add3~52 heartbeat:u1|d2_next[2]~41 heartbeat:u1|d2_reg[2] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X25_Y14 X37_Y27 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X25_Y14 to location X37_Y27" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "28 " "Warning: Found 28 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssega\[0\] 0 " "Info: Pin \"ssega\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssega\[1\] 0 " "Info: Pin \"ssega\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssega\[2\] 0 " "Info: Pin \"ssega\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssega\[3\] 0 " "Info: Pin \"ssega\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssega\[4\] 0 " "Info: Pin \"ssega\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssega\[5\] 0 " "Info: Pin \"ssega\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssega\[6\] 0 " "Info: Pin \"ssega\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegb\[0\] 0 " "Info: Pin \"ssegb\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegb\[1\] 0 " "Info: Pin \"ssegb\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegb\[2\] 0 " "Info: Pin \"ssegb\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegb\[3\] 0 " "Info: Pin \"ssegb\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegb\[4\] 0 " "Info: Pin \"ssegb\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegb\[5\] 0 " "Info: Pin \"ssegb\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegb\[6\] 0 " "Info: Pin \"ssegb\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegc\[0\] 0 " "Info: Pin \"ssegc\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegc\[1\] 0 " "Info: Pin \"ssegc\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegc\[2\] 0 " "Info: Pin \"ssegc\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegc\[3\] 0 " "Info: Pin \"ssegc\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegc\[4\] 0 " "Info: Pin \"ssegc\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegc\[5\] 0 " "Info: Pin \"ssegc\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegc\[6\] 0 " "Info: Pin \"ssegc\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegd\[0\] 0 " "Info: Pin \"ssegd\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegd\[1\] 0 " "Info: Pin \"ssegd\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegd\[2\] 0 " "Info: Pin \"ssegd\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegd\[3\] 0 " "Info: Pin \"ssegd\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegd\[4\] 0 " "Info: Pin \"ssegd\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegd\[5\] 0 " "Info: Pin \"ssegd\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ssegd\[6\] 0 " "Info: Pin \"ssegd\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "16 " "Warning: Following 16 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ssega\[0\] VCC " "Info: Pin ssega\[0\] has VCC driving its datain port" {  } { { "c:/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80sp1/quartus/bin/pin_planner.ppl" { ssega[0] } } } { "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ssega\[0\]" } } } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ssega[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ssega\[3\] VCC " "Info: Pin ssega\[3\] has VCC driving its datain port" {  } { { "c:/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80sp1/quartus/bin/pin_planner.ppl" { ssega[3] } } } { "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ssega\[3\]" } } } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ssega[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ssega\[4\] VCC " "Info: Pin ssega\[4\] has VCC driving its datain port" {  } { { "c:/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80sp1/quartus/bin/pin_planner.ppl" { ssega[4] } } } { "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ssega\[4\]" } } } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ssega[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ssega\[5\] VCC " "Info: Pin ssega\[5\] has VCC driving its datain port" {  } { { "c:/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80sp1/quartus/bin/pin_planner.ppl" { ssega[5] } } } { "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ssega\[5\]" } } } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ssega[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ssega\[6\] VCC " "Info: Pin ssega\[6\] has VCC driving its datain port" {  } { { "c:/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80sp1/quartus/bin/pin_planner.ppl" { ssega[6] } } } { "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ssega\[6\]" } } } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ssega[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ssegb\[0\] VCC " "Info: Pin ssegb\[0\] has VCC driving its datain port" {  } { { "c:/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80sp1/quartus/bin/pin_planner.ppl" { ssegb[0] } } } { "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ssegb\[0\]" } } } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ssegb[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ssegb\[3\] VCC " "Info: Pin ssegb\[3\] has VCC driving its datain port" {  } { { "c:/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80sp1/quartus/bin/pin_planner.ppl" { ssegb[3] } } } { "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ssegb\[3\]" } } } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ssegb[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ssegb\[6\] VCC " "Info: Pin ssegb\[6\] has VCC driving its datain port" {  } { { "c:/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80sp1/quartus/bin/pin_planner.ppl" { ssegb[6] } } } { "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ssegb\[6\]" } } } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ssegb[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ssegc\[0\] VCC " "Info: Pin ssegc\[0\] has VCC driving its datain port" {  } { { "c:/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80sp1/quartus/bin/pin_planner.ppl" { ssegc[0] } } } { "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ssegc\[0\]" } } } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ssegc[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ssegc\[3\] VCC " "Info: Pin ssegc\[3\] has VCC driving its datain port" {  } { { "c:/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80sp1/quartus/bin/pin_planner.ppl" { ssegc[3] } } } { "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ssegc\[3\]" } } } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ssegc[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ssegc\[6\] VCC " "Info: Pin ssegc\[6\] has VCC driving its datain port" {  } { { "c:/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80sp1/quartus/bin/pin_planner.ppl" { ssegc[6] } } } { "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ssegc\[6\]" } } } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ssegc[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ssegd\[0\] VCC " "Info: Pin ssegd\[0\] has VCC driving its datain port" {  } { { "c:/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80sp1/quartus/bin/pin_planner.ppl" { ssegd[0] } } } { "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ssegd\[0\]" } } } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ssegd[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ssegd\[1\] VCC " "Info: Pin ssegd\[1\] has VCC driving its datain port" {  } { { "c:/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80sp1/quartus/bin/pin_planner.ppl" { ssegd[1] } } } { "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ssegd\[1\]" } } } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ssegd[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ssegd\[2\] VCC " "Info: Pin ssegd\[2\] has VCC driving its datain port" {  } { { "c:/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80sp1/quartus/bin/pin_planner.ppl" { ssegd[2] } } } { "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ssegd\[2\]" } } } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ssegd[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ssegd\[3\] VCC " "Info: Pin ssegd\[3\] has VCC driving its datain port" {  } { { "c:/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80sp1/quartus/bin/pin_planner.ppl" { ssegd[3] } } } { "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ssegd\[3\]" } } } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ssegd[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ssegd\[6\] VCC " "Info: Pin ssegd\[6\] has VCC driving its datain port" {  } { { "c:/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80sp1/quartus/bin/pin_planner.ppl" { ssegd[6] } } } { "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ssegd\[6\]" } } } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ssegd[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "194 " "Info: Peak virtual memory: 194 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 29 16:34:56 2008 " "Info: Processing ended: Wed Oct 29 16:34:56 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Info: Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}