lab7.fit.qmsg

用VHDL编译的源代码

{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 0}  } {  } 0 0 "Finished register packing" 0 0 "" 0 0}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.503 ns register register " "Info: Estimated most critical path is register to register delay of 5.503 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns heartbeat:u1\|ms_reg\[23\] 1 REG LAB_X30_Y23 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X30_Y23; Fanout = 3; REG Node = 'heartbeat:u1\|ms_reg\[23\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { heartbeat:u1|ms_reg[23] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.135 ns) + CELL(0.177 ns) 1.312 ns heartbeat:u1\|Equal0~292 2 COMB LAB_X29_Y24 1 " "Info: 2: + IC(1.135 ns) + CELL(0.177 ns) = 1.312 ns; Loc. = LAB_X29_Y24; Fanout = 1; COMB Node = 'heartbeat:u1\|Equal0~292'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.312 ns" { heartbeat:u1|ms_reg[23] heartbeat:u1|Equal0~292 } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.154 ns) + CELL(0.521 ns) 1.987 ns heartbeat:u1\|Equal0~293 3 COMB LAB_X29_Y24 1 " "Info: 3: + IC(0.154 ns) + CELL(0.521 ns) = 1.987 ns; Loc. = LAB_X29_Y24; Fanout = 1; COMB Node = 'heartbeat:u1\|Equal0~293'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.675 ns" { heartbeat:u1|Equal0~292 heartbeat:u1|Equal0~293 } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.178 ns) 2.663 ns heartbeat:u1\|Equal0~294 4 COMB LAB_X29_Y24 20 " "Info: 4: + IC(0.498 ns) + CELL(0.178 ns) = 2.663 ns; Loc. = LAB_X29_Y24; Fanout = 20; COMB Node = 'heartbeat:u1\|Equal0~294'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { heartbeat:u1|Equal0~293 heartbeat:u1|Equal0~294 } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.013 ns) + CELL(0.517 ns) 4.193 ns heartbeat:u1\|Add3~49 5 COMB LAB_X27_Y24 1 " "Info: 5: + IC(1.013 ns) + CELL(0.517 ns) = 4.193 ns; Loc. = LAB_X27_Y24; Fanout = 1; COMB Node = 'heartbeat:u1\|Add3~49'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.530 ns" { heartbeat:u1|Equal0~294 heartbeat:u1|Add3~49 } "NODE_NAME" } } { "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" "" { Text "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" 1244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.273 ns heartbeat:u1\|Add3~51 6 COMB LAB_X27_Y24 2 " "Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 4.273 ns; Loc. = LAB_X27_Y24; Fanout = 2; COMB Node = 'heartbeat:u1\|Add3~51'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { heartbeat:u1|Add3~49 heartbeat:u1|Add3~51 } "NODE_NAME" } } { "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" "" { Text "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" 1244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 4.731 ns heartbeat:u1\|Add3~52 7 COMB LAB_X27_Y24 1 " "Info: 7: + IC(0.000 ns) + CELL(0.458 ns) = 4.731 ns; Loc. = LAB_X27_Y24; Fanout = 1; COMB Node = 'heartbeat:u1\|Add3~52'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { heartbeat:u1|Add3~51 heartbeat:u1|Add3~52 } "NODE_NAME" } } { "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" "" { Text "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" 1244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.131 ns) + CELL(0.545 ns) 5.407 ns heartbeat:u1\|d2_next\[2\]~41 8 COMB LAB_X27_Y24 1 " "Info: 8: + IC(0.131 ns) + CELL(0.545 ns) = 5.407 ns; Loc. = LAB_X27_Y24; Fanout = 1; COMB Node = 'heartbeat:u1\|d2_next\[2\]~41'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { heartbeat:u1|Add3~52 heartbeat:u1|d2_next[2]~41 } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 5.503 ns heartbeat:u1\|d2_reg\[2\] 9 REG LAB_X27_Y24 5 " "Info: 9: + IC(0.000 ns) + CELL(0.096 ns) = 5.503 ns; Loc. = LAB_X27_Y24; Fanout = 5; REG Node = 'heartbeat:u1\|d2_reg\[2\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { heartbeat:u1|d2_next[2]~41 heartbeat:u1|d2_reg[2] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.572 ns ( 46.74 % ) " "Info: Total cell delay = 2.572 ns ( 46.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.931 ns ( 53.26 % ) " "Info: Total interconnect delay = 2.931 ns ( 53.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "5.503 ns" { heartbeat:u1|ms_reg[23] heartbeat:u1|Equal0~292 heartbeat:u1|Equal0~293 heartbeat:u1|Equal0~294 heartbeat:u1|Add3~49 heartbeat:u1|Add3~51 heartbeat:u1|Add3~52 heartbeat:u1|d2_next[2]~41 heartbeat:u1|d2_reg[2] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}