prev_cmp_lab7.tan.qmsg

用VHDL编译的源代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1 register heartbeat:u1\|ms_reg\[20\] register heartbeat:u1\|d0_reg\[2\] 175.19 MHz 5.708 ns Internal " "Info: Clock \"clk1\" has Internal fmax of 175.19 MHz between source register \"heartbeat:u1\|ms_reg\[20\]\" and destination register \"heartbeat:u1\|d0_reg\[2\]\" (period= 5.708 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.472 ns + Longest register register " "Info: + Longest register to register delay is 5.472 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns heartbeat:u1\|ms_reg\[20\] 1 REG LCFF_X30_Y23_N29 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y23_N29; Fanout = 3; REG Node = 'heartbeat:u1\|ms_reg\[20\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { heartbeat:u1|ms_reg[20] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.491 ns) 0.856 ns heartbeat:u1\|Equal0~286 2 COMB LCCOMB_X30_Y23_N30 1 " "Info: 2: + IC(0.365 ns) + CELL(0.491 ns) = 0.856 ns; Loc. = LCCOMB_X30_Y23_N30; Fanout = 1; COMB Node = 'heartbeat:u1\|Equal0~286'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.856 ns" { heartbeat:u1|ms_reg[20] heartbeat:u1|Equal0~286 } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.903 ns) + CELL(0.322 ns) 2.081 ns heartbeat:u1\|Equal0~288 3 COMB LCCOMB_X29_Y24_N14 1 " "Info: 3: + IC(0.903 ns) + CELL(0.322 ns) = 2.081 ns; Loc. = LCCOMB_X29_Y24_N14; Fanout = 1; COMB Node = 'heartbeat:u1\|Equal0~288'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.225 ns" { heartbeat:u1|Equal0~286 heartbeat:u1|Equal0~288 } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.302 ns) + CELL(0.322 ns) 2.705 ns heartbeat:u1\|Equal0~294 4 COMB LCCOMB_X29_Y24_N30 20 " "Info: 4: + IC(0.302 ns) + CELL(0.322 ns) = 2.705 ns; Loc. = LCCOMB_X29_Y24_N30; Fanout = 20; COMB Node = 'heartbeat:u1\|Equal0~294'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.624 ns" { heartbeat:u1|Equal0~288 heartbeat:u1|Equal0~294 } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.795 ns) + CELL(0.517 ns) 4.017 ns heartbeat:u1\|Add1~49 5 COMB LCCOMB_X29_Y24_N18 2 " "Info: 5: + IC(0.795 ns) + CELL(0.517 ns) = 4.017 ns; Loc. = LCCOMB_X29_Y24_N18; Fanout = 2; COMB Node = 'heartbeat:u1\|Add1~49'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.312 ns" { heartbeat:u1|Equal0~294 heartbeat:u1|Add1~49 } "NODE_NAME" } } { "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" "" { Text "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" 1244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.097 ns heartbeat:u1\|Add1~51 6 COMB LCCOMB_X29_Y24_N20 2 " "Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 4.097 ns; Loc. = LCCOMB_X29_Y24_N20; Fanout = 2; COMB Node = 'heartbeat:u1\|Add1~51'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { heartbeat:u1|Add1~49 heartbeat:u1|Add1~51 } "NODE_NAME" } } { "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" "" { Text "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" 1244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 4.555 ns heartbeat:u1\|Add1~52 7 COMB LCCOMB_X29_Y24_N22 1 " "Info: 7: + IC(0.000 ns) + CELL(0.458 ns) = 4.555 ns; Loc. = LCCOMB_X29_Y24_N22; Fanout = 1; COMB Node = 'heartbeat:u1\|Add1~52'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { heartbeat:u1|Add1~51 heartbeat:u1|Add1~52 } "NODE_NAME" } } { "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" "" { Text "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" 1244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.521 ns) 5.376 ns heartbeat:u1\|d0_next\[2\]~50 8 COMB LCCOMB_X29_Y24_N8 1 " "Info: 8: + IC(0.300 ns) + CELL(0.521 ns) = 5.376 ns; Loc. = LCCOMB_X29_Y24_N8; Fanout = 1; COMB Node = 'heartbeat:u1\|d0_next\[2\]~50'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.821 ns" { heartbeat:u1|Add1~52 heartbeat:u1|d0_next[2]~50 } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 5.472 ns heartbeat:u1\|d0_reg\[2\] 9 REG LCFF_X29_Y24_N9 4 " "Info: 9: + IC(0.000 ns) + CELL(0.096 ns) = 5.472 ns; Loc. = LCFF_X29_Y24_N9; Fanout = 4; REG Node = 'heartbeat:u1\|d0_reg\[2\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { heartbeat:u1|d0_next[2]~50 heartbeat:u1|d0_reg[2] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.807 ns ( 51.30 % ) " "Info: Total cell delay = 2.807 ns ( 51.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.665 ns ( 48.70 % ) " "Info: Total interconnect delay = 2.665 ns ( 48.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "5.472 ns" { heartbeat:u1|ms_reg[20] heartbeat:u1|Equal0~286 heartbeat:u1|Equal0~288 heartbeat:u1|Equal0~294 heartbeat:u1|Add1~49 heartbeat:u1|Add1~51 heartbeat:u1|Add1~52 heartbeat:u1|d0_next[2]~50 heartbeat:u1|d0_reg[2] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "5.472 ns" { heartbeat:u1|ms_reg[20] {} heartbeat:u1|Equal0~286 {} heartbeat:u1|Equal0~288 {} heartbeat:u1|Equal0~294 {} heartbeat:u1|Add1~49 {} heartbeat:u1|Add1~51 {} heartbeat:u1|Add1~52 {} heartbeat:u1|d0_next[2]~50 {} heartbeat:u1|d0_reg[2] {} } { 0.000ns 0.365ns 0.903ns 0.302ns 0.795ns 0.000ns 0.000ns 0.300ns 0.000ns } { 0.000ns 0.491ns 0.322ns 0.322ns 0.517ns 0.080ns 0.458ns 0.521ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.003 ns - Smallest " "Info: - Smallest clock skew is 0.003 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.858 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1\" to destination register is 2.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk1 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk1'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk1~clkctrl 2 COMB CLKCTRL_G2 36 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 36; COMB Node = 'clk1~clkctrl'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk1 clk1~clkctrl } "NODE_NAME" } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.602 ns) 2.858 ns heartbeat:u1\|d0_reg\[2\] 3 REG LCFF_X29_Y24_N9 4 " "Info: 3: + IC(0.992 ns) + CELL(0.602 ns) = 2.858 ns; Loc. = LCFF_X29_Y24_N9; Fanout = 4; REG Node = 'heartbeat:u1\|d0_reg\[2\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.594 ns" { clk1~clkctrl heartbeat:u1|d0_reg[2] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.96 % ) " "Info: Total cell delay = 1.628 ns ( 56.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.230 ns ( 43.04 % ) " "Info: Total interconnect delay = 1.230 ns ( 43.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.858 ns" { clk1 clk1~clkctrl heartbeat:u1|d0_reg[2] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.858 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} heartbeat:u1|d0_reg[2] {} } { 0.000ns 0.000ns 0.238ns 0.992ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.855 ns - Longest register " "Info: - Longest clock path from clock \"clk1\" to source register is 2.855 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk1 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk1'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk1~clkctrl 2 COMB CLKCTRL_G2 36 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 36; COMB Node = 'clk1~clkctrl'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk1 clk1~clkctrl } "NODE_NAME" } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.989 ns) + CELL(0.602 ns) 2.855 ns heartbeat:u1\|ms_reg\[20\] 3 REG LCFF_X30_Y23_N29 3 " "Info: 3: + IC(0.989 ns) + CELL(0.602 ns) = 2.855 ns; Loc. = LCFF_X30_Y23_N29; Fanout = 3; REG Node = 'heartbeat:u1\|ms_reg\[20\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.591 ns" { clk1~clkctrl heartbeat:u1|ms_reg[20] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.02 % ) " "Info: Total cell delay = 1.628 ns ( 57.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.227 ns ( 42.98 % ) " "Info: Total interconnect delay = 1.227 ns ( 42.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.855 ns" { clk1 clk1~clkctrl heartbeat:u1|ms_reg[20] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.855 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} heartbeat:u1|ms_reg[20] {} } { 0.000ns 0.000ns 0.238ns 0.989ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.858 ns" { clk1 clk1~clkctrl heartbeat:u1|d0_reg[2] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.858 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} heartbeat:u1|d0_reg[2] {} } { 0.000ns 0.000ns 0.238ns 0.992ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.855 ns" { clk1 clk1~clkctrl heartbeat:u1|ms_reg[20] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.855 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} heartbeat:u1|ms_reg[20] {} } { 0.000ns 0.000ns 0.238ns 0.989ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "5.472 ns" { heartbeat:u1|ms_reg[20] heartbeat:u1|Equal0~286 heartbeat:u1|Equal0~288 heartbeat:u1|Equal0~294 heartbeat:u1|Add1~49 heartbeat:u1|Add1~51 heartbeat:u1|Add1~52 heartbeat:u1|d0_next[2]~50 heartbeat:u1|d0_reg[2] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "5.472 ns" { heartbeat:u1|ms_reg[20] {} heartbeat:u1|Equal0~286 {} heartbeat:u1|Equal0~288 {} heartbeat:u1|Equal0~294 {} heartbeat:u1|Add1~49 {} heartbeat:u1|Add1~51 {} heartbeat:u1|Add1~52 {} heartbeat:u1|d0_next[2]~50 {} heartbeat:u1|d0_reg[2] {} } { 0.000ns 0.365ns 0.903ns 0.302ns 0.795ns 0.000ns 0.000ns 0.300ns 0.000ns } { 0.000ns 0.491ns 0.322ns 0.322ns 0.517ns 0.080ns 0.458ns 0.521ns 0.096ns } "" } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.858 ns" { clk1 clk1~clkctrl heartbeat:u1|d0_reg[2] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.858 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} heartbeat:u1|d0_reg[2] {} } { 0.000ns 0.000ns 0.238ns 0.992ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.855 ns" { clk1 clk1~clkctrl heartbeat:u1|ms_reg[20] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.855 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} heartbeat:u1|ms_reg[20] {} } { 0.000ns 0.000ns 0.238ns 0.989ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk1 ssega\[1\] heartbeat:u1\|d0_reg\[0\] 10.927 ns register " "Info: tco from clock \"clk1\" to destination pin \"ssega\[1\]\" through register \"heartbeat:u1\|d0_reg\[0\]\" is 10.927 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.858 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to source register is 2.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk1 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk1'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk1~clkctrl 2 COMB CLKCTRL_G2 36 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 36; COMB Node = 'clk1~clkctrl'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk1 clk1~clkctrl } "NODE_NAME" } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.602 ns) 2.858 ns heartbeat:u1\|d0_reg\[0\] 3 REG LCFF_X29_Y24_N19 12 " "Info: 3: + IC(0.992 ns) + CELL(0.602 ns) = 2.858 ns; Loc. = LCFF_X29_Y24_N19; Fanout = 12; REG Node = 'heartbeat:u1\|d0_reg\[0\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.594 ns" { clk1~clkctrl heartbeat:u1|d0_reg[0] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.96 % ) " "Info: Total cell delay = 1.628 ns ( 56.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.230 ns ( 43.04 % ) " "Info: Total interconnect delay = 1.230 ns ( 43.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.858 ns" { clk1 clk1~clkctrl heartbeat:u1|d0_reg[0] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.858 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} heartbeat:u1|d0_reg[0] {} } { 0.000ns 0.000ns 0.238ns 0.992ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.792 ns + Longest register pin " "Info: + Longest register to pin delay is 7.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns heartbeat:u1\|d0_reg\[0\] 1 REG LCFF_X29_Y24_N19 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y24_N19; Fanout = 12; REG Node = 'heartbeat:u1\|d0_reg\[0\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { heartbeat:u1|d0_reg[0] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.455 ns) 1.461 ns bin2led0:u2\|Mux1~27 2 COMB LCCOMB_X27_Y24_N0 2 " "Info: 2: + IC(1.006 ns) + CELL(0.455 ns) = 1.461 ns; Loc. = LCCOMB_X27_Y24_N0; Fanout = 2; COMB Node = 'bin2led0:u2\|Mux1~27'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.461 ns" { heartbeat:u1|d0_reg[0] bin2led0:u2|Mux1~27 } "NODE_NAME" } } { "bin2led0.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/bin2led0.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.491 ns) + CELL(2.840 ns) 7.792 ns ssega\[1\] 3 PIN PIN_J1 0 " "Info: 3: + IC(3.491 ns) + CELL(2.840 ns) = 7.792 ns; Loc. = PIN_J1; Fanout = 0; PIN Node = 'ssega\[1\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.331 ns" { bin2led0:u2|Mux1~27 ssega[1] } "NODE_NAME" } } { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.295 ns ( 42.29 % ) " "Info: Total cell delay = 3.295 ns ( 42.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.497 ns ( 57.71 % ) " "Info: Total interconnect delay = 4.497 ns ( 57.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "7.792 ns" { heartbeat:u1|d0_reg[0] bin2led0:u2|Mux1~27 ssega[1] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "7.792 ns" { heartbeat:u1|d0_reg[0] {} bin2led0:u2|Mux1~27 {} ssega[1] {} } { 0.000ns 1.006ns 3.491ns } { 0.000ns 0.455ns 2.840ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.858 ns" { clk1 clk1~clkctrl heartbeat:u1|d0_reg[0] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.858 ns" { clk1 {} clk1~combout {} clk1~clkctrl {} heartbeat:u1|d0_reg[0] {} } { 0.000ns 0.000ns 0.238ns 0.992ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "7.792 ns" { heartbeat:u1|d0_reg[0] bin2led0:u2|Mux1~27 ssega[1] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "7.792 ns" { heartbeat:u1|d0_reg[0] {} bin2led0:u2|Mux1~27 {} ssega[1] {} } { 0.000ns 1.006ns 3.491ns } { 0.000ns 0.455ns 2.840ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "124 " "Info: Peak virtual memory: 124 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 29 16:35:11 2008 " "Info: Processing ended: Wed Oct 29 16:35:11 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}