prev_cmp_lab7.qmsg

用VHDL编译的源代码

{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "194 " "Info: Peak virtual memory: 194 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 29 16:34:56 2008 " "Info: Processing ended: Wed Oct 29 16:34:56 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Info: Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Web Edition " "Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 29 16:34:58 2008 " "Info: Processing started: Wed Oct 29 16:34:58 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off lab7 -c lab7 " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off lab7 -c lab7" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "172 " "Info: Peak virtual memory: 172 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 29 16:35:06 2008 " "Info: Processing ended: Wed Oct 29 16:35:06 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Web Edition " "Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 29 16:35:08 2008 " "Info: Processing started: Wed Oct 29 16:35:08 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off lab7 -c lab7 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lab7 -c lab7 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node \"clk1\" is an undefined clock" {  } { { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 5 -1 0 } } { "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1 register heartbeat:u1\|ms_reg\[20\] register heartbeat:u1\|d0_reg\[2\] 175.19 MHz 5.708 ns Internal " "Info: Clock \"clk1\" has Internal fmax of 175.19 MHz between source register \"heartbeat:u1\|ms_reg\[20\]\" and destination register \"heartbeat:u1\|d0_reg\[2\]\" (period= 5.708 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.472 ns + Longest register register " "Info: + Longest register to register delay is 5.472 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns heartbeat:u1\|ms_reg\[20\] 1 REG LCFF_X30_Y23_N29 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y23_N29; Fanout = 3; REG Node = 'heartbeat:u1\|ms_reg\[20\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { heartbeat:u1|ms_reg[20] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.491 ns) 0.856 ns heartbeat:u1\|Equal0~286 2 COMB LCCOMB_X30_Y23_N30 1 " "Info: 2: + IC(0.365 ns) + CELL(0.491 ns) = 0.856 ns; Loc. = LCCOMB_X30_Y23_N30; Fanout = 1; COMB Node = 'heartbeat:u1\|Equal0~286'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.856 ns" { heartbeat:u1|ms_reg[20] heartbeat:u1|Equal0~286 } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.903 ns) + CELL(0.322 ns) 2.081 ns heartbeat:u1\|Equal0~288 3 COMB LCCOMB_X29_Y24_N14 1 " "Info: 3: + IC(0.903 ns) + CELL(0.322 ns) = 2.081 ns; Loc. = LCCOMB_X29_Y24_N14; Fanout = 1; COMB Node = 'heartbeat:u1\|Equal0~288'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.225 ns" { heartbeat:u1|Equal0~286 heartbeat:u1|Equal0~288 } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.302 ns) + CELL(0.322 ns) 2.705 ns heartbeat:u1\|Equal0~294 4 COMB LCCOMB_X29_Y24_N30 20 " "Info: 4: + IC(0.302 ns) + CELL(0.322 ns) = 2.705 ns; Loc. = LCCOMB_X29_Y24_N30;