lab7.map.qmsg

用VHDL编译的源代码

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2led1 bin2led1:u3 " "Info: Elaborating entity \"bin2led1\" for hierarchy \"bin2led1:u3\"" {  } { { "lab7.vhd" "u3" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 53 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "bin2led2.vhd 2 1 " "Warning: Using design file bin2led2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bin2led2-arch " "Info: Found design unit 1: bin2led2-arch" {  } { { "bin2led2.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/bin2led2.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 bin2led2 " "Info: Found entity 1: bin2led2" {  } { { "bin2led2.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/bin2led2.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2led2 bin2led2:u4 " "Info: Elaborating entity \"bin2led2\" for hierarchy \"bin2led2:u4\"" {  } { { "lab7.vhd" "u4" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 54 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "bin2led3.vhd 2 1 " "Warning: Using design file bin2led3.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bin2led3-arch " "Info: Found design unit 1: bin2led3-arch" {  } { { "bin2led3.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/bin2led3.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 bin2led3 " "Info: Found entity 1: bin2led3" {  } { { "bin2led3.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/bin2led3.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2led3 bin2led3:u5 " "Info: Elaborating entity \"bin2led3\" for hierarchy \"bin2led3:u5\"" {  } { { "lab7.vhd" "u5" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 55 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "heartbeat:u1\|d3_reg\[0\] heartbeat:u1\|d0_reg\[0\] " "Info (13350): Duplicate register \"heartbeat:u1\|d3_reg\[0\]\" merged to single register \"heartbeat:u1\|d0_reg\[0\]\"" {  } { { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "heartbeat:u1\|d1_reg\[0\] heartbeat:u1\|d0_reg\[0\] " "Info (13350): Duplicate register \"heartbeat:u1\|d1_reg\[0\]\" merged to single register \"heartbeat:u1\|d0_reg\[0\]\"" {  } { { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "heartbeat:u1\|d2_reg\[0\] heartbeat:u1\|d0_reg\[0\] " "Info (13350): Duplicate register \"heartbeat:u1\|d2_reg\[0\]\" merged to single register \"heartbeat:u1\|d0_reg\[0\]\"" {  } { { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "heartbeat:u1\|d2_reg\[1\] heartbeat:u1\|d0_reg\[1\] " "Info (13350): Duplicate register \"heartbeat:u1\|d2_reg\[1\]\" merged to single register \"heartbeat:u1\|d0_reg\[1\]\"" {  } { { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "heartbeat:u1\|d3_reg\[1\] heartbeat:u1\|d0_reg\[1\] " "Info (13350): Duplicate register \"heartbeat:u1\|d3_reg\[1\]\" merged to single register \"heartbeat:u1\|d0_reg\[1\]\"" {  } { { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "heartbeat:u1\|d1_reg\[1\] heartbeat:u1\|d0_reg\[1\] " "Info (13350): Duplicate register \"heartbeat:u1\|d1_reg\[1\]\" merged to single register \"heartbeat:u1\|d0_reg\[1\]\"" {  } { { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat.vhd" 24 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "ssega\[0\] VCC " "Warning (13410): Pin \"ssega\[0\]\" is stuck at VCC" {  } { { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ssega\[3\] VCC " "Warning (13410): Pin \"ssega\[3\]\" is stuck at VCC" {  } { { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ssega\[4\] VCC " "Warning (13410): Pin \"ssega\[4\]\" is stuck at VCC" {  } { { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ssega\[5\] VCC " "Warning (13410): Pin \"ssega\[5\]\" is stuck at VCC" {  } { { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ssega\[6\] VCC " "Warning (13410): Pin \"ssega\[6\]\" is stuck at VCC" {  } { { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ssegb\[0\] VCC " "Warning (13410): Pin \"ssegb\[0\]\" is stuck at VCC" {  } { { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ssegb\[3\] VCC " "Warning (13410): Pin \"ssegb\[3\]\" is stuck at VCC" {  } { { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ssegb\[6\] VCC " "Warning (13410): Pin \"ssegb\[6\]\" is stuck at VCC" {  } { { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ssegc\[0\] VCC " "Warning (13410): Pin \"ssegc\[0\]\" is stuck at VCC" {  } { { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ssegc\[3\] VCC " "Warning (13410): Pin \"ssegc\[3\]\" is stuck at VCC" {  } { { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ssegc\[6\] VCC " "Warning (13410): Pin \"ssegc\[6\]\" is stuck at VCC" {  } { { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ssegd\[0\] VCC " "Warning (13410): Pin \"ssegd\[0\]\" is stuck at VCC" {  } { { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ssegd\[1\] VCC " "Warning (13410): Pin \"ssegd\[1\]\" is stuck at VCC" {  } { { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ssegd\[2\] VCC " "Warning (13410): Pin \"ssegd\[2\]\" is stuck at VCC" {  } { { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ssegd\[3\] VCC " "Warning (13410): Pin \"ssegd\[3\]\" is stuck at VCC" {  } { { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ssegd\[6\] VCC " "Warning (13410): Pin \"ssegd\[6\]\" is stuck at VCC" {  } { { "lab7.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vhd" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "105 " "Info: Implemented 105 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Info: Implemented 28 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "76 " "Info: Implemented 76 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 22 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 22 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "180 " "Info: Peak virtual memory: 180 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 29 16:36:06 2008 " "Info: Processing ended: Wed Oct 29 16:36:06 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}