lab7.sim.rpt

用VHDL编译的源代码

; |lab7|heartbeat:u1|Equal0~45     ; |lab7|heartbeat:u1|Equal0~45     ; combout          ;
; |lab7|heartbeat:u1|d0_next[2]~83 ; |lab7|heartbeat:u1|d0_next[2]~83 ; combout          ;
; |lab7|heartbeat:u1|d0_next[2]~84 ; |lab7|heartbeat:u1|d0_next[2]~84 ; combout          ;
; |lab7|heartbeat:u1|d1_next[2]~73 ; |lab7|heartbeat:u1|d1_next[2]~73 ; combout          ;
; |lab7|heartbeat:u1|d2_next[2]~73 ; |lab7|heartbeat:u1|d2_next[2]~73 ; combout          ;
; |lab7|heartbeat:u1|d3_next[2]~73 ; |lab7|heartbeat:u1|d3_next[2]~73 ; combout          ;
; |lab7|heartbeat:u1|ms_next[2]~35 ; |lab7|heartbeat:u1|ms_next[2]~35 ; combout          ;
; |lab7|heartbeat:u1|ms_next[1]~36 ; |lab7|heartbeat:u1|ms_next[1]~36 ; combout          ;
; |lab7|heartbeat:u1|ms_reg[0]~8   ; |lab7|heartbeat:u1|ms_reg[0]~8   ; combout          ;
; |lab7|ssega[1]                   ; |lab7|ssega[1]                   ; padio            ;
; |lab7|ssega[2]                   ; |lab7|ssega[2]                   ; padio            ;
; |lab7|ssegb[1]                   ; |lab7|ssegb[1]                   ; padio            ;
; |lab7|ssegb[2]                   ; |lab7|ssegb[2]                   ; padio            ;
; |lab7|ssegb[4]                   ; |lab7|ssegb[4]                   ; padio            ;
; |lab7|ssegb[5]                   ; |lab7|ssegb[5]                   ; padio            ;
; |lab7|ssegc[1]                   ; |lab7|ssegc[1]                   ; padio            ;
; |lab7|ssegc[2]                   ; |lab7|ssegc[2]                   ; padio            ;
; |lab7|ssegc[4]                   ; |lab7|ssegc[4]                   ; padio            ;
; |lab7|ssegc[5]                   ; |lab7|ssegc[5]                   ; padio            ;
; |lab7|ssegd[4]                   ; |lab7|ssegd[4]                   ; padio            ;
; |lab7|ssegd[5]                   ; |lab7|ssegd[5]                   ; padio            ;
; |lab7|clk1                       ; |lab7|clk1~corein                ; combout          ;
; |lab7|clk1~clkctrl               ; |lab7|clk1~clkctrl               ; outclk           ;
+----------------------------------+----------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                       ;
+------------------------------+------------------------------+------------------+
; Node Name                    ; Output Port Name             ; Output Port Type ;
+------------------------------+------------------------------+------------------+
; |lab7|heartbeat:u1|Add1~52   ; |lab7|heartbeat:u1|Add1~53   ; cout             ;
; |lab7|heartbeat:u1|Add1~54   ; |lab7|heartbeat:u1|Add1~54   ; combout          ;
; |lab7|heartbeat:u1|Add2~52   ; |lab7|heartbeat:u1|Add2~53   ; cout             ;
; |lab7|heartbeat:u1|Add2~54   ; |lab7|heartbeat:u1|Add2~54   ; combout          ;
; |lab7|heartbeat:u1|Add3~52   ; |lab7|heartbeat:u1|Add3~53   ; cout             ;
; |lab7|heartbeat:u1|Add3~54   ; |lab7|heartbeat:u1|Add3~54   ; combout          ;
; |lab7|heartbeat:u1|Add4~52   ; |lab7|heartbeat:u1|Add4~53   ; cout             ;
; |lab7|heartbeat:u1|Add4~54   ; |lab7|heartbeat:u1|Add4~54   ; combout          ;
; |lab7|heartbeat:u1|d0_reg[3] ; |lab7|heartbeat:u1|d0_reg[3] ; regout           ;
; |lab7|heartbeat:u1|d0_reg[2] ; |lab7|heartbeat:u1|d0_reg[2] ; regout           ;
; |lab7|heartbeat:u1|d1_reg[3] ; |lab7|heartbeat:u1|d1_reg[3] ; regout           ;
; |lab7|heartbeat:u1|d1_reg[2] ; |lab7|heartbeat:u1|d1_reg[2] ; regout           ;
; |lab7|heartbeat:u1|d2_reg[3] ; |lab7|heartbeat:u1|d2_reg[3] ; regout           ;
; |lab7|heartbeat:u1|d2_reg[2] ; |lab7|heartbeat:u1|d2_reg[2] ; regout           ;
; |lab7|heartbeat:u1|d3_reg[3] ; |lab7|heartbeat:u1|d3_reg[3] ; regout           ;
; |lab7|heartbeat:u1|d3_reg[2] ; |lab7|heartbeat:u1|d3_reg[2] ; regout           ;
; |lab7|ssega[0]               ; |lab7|ssega[0]               ; padio            ;
; |lab7|ssega[3]               ; |lab7|ssega[3]               ; padio            ;
; |lab7|ssega[4]               ; |lab7|ssega[4]               ; padio            ;
; |lab7|ssega[5]               ; |lab7|ssega[5]               ; padio            ;
; |lab7|ssega[6]               ; |lab7|ssega[6]               ; padio            ;
; |lab7|ssegb[0]               ; |lab7|ssegb[0]               ; padio            ;
; |lab7|ssegb[3]               ; |lab7|ssegb[3]               ; padio            ;
; |lab7|ssegb[6]               ; |lab7|ssegb[6]               ; padio            ;
; |lab7|ssegc[0]               ; |lab7|ssegc[0]               ; padio            ;
; |lab7|ssegc[3]               ; |lab7|ssegc[3]               ; padio            ;
; |lab7|ssegc[6]               ; |lab7|ssegc[6]               ; padio            ;
; |lab7|ssegd[0]               ; |lab7|ssegd[0]               ; padio            ;
; |lab7|ssegd[1]               ; |lab7|ssegd[1]               ; padio            ;
; |lab7|ssegd[2]               ; |lab7|ssegd[2]               ; padio            ;
; |lab7|ssegd[3]               ; |lab7|ssegd[3]               ; padio            ;
; |lab7|ssegd[6]               ; |lab7|ssegd[6]               ; padio            ;
+------------------------------+------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                       ;
+------------------------------+------------------------------+------------------+
; Node Name                    ; Output Port Name             ; Output Port Type ;
+------------------------------+------------------------------+------------------+
; |lab7|heartbeat:u1|Add1~52   ; |lab7|heartbeat:u1|Add1~53   ; cout             ;
; |lab7|heartbeat:u1|Add1~54   ; |lab7|heartbeat:u1|Add1~54   ; combout          ;
; |lab7|heartbeat:u1|Add2~52   ; |lab7|heartbeat:u1|Add2~53   ; cout             ;
; |lab7|heartbeat:u1|Add2~54   ; |lab7|heartbeat:u1|Add2~54   ; combout          ;
; |lab7|heartbeat:u1|Add3~52   ; |lab7|heartbeat:u1|Add3~53   ; cout             ;
; |lab7|heartbeat:u1|Add3~54   ; |lab7|heartbeat:u1|Add3~54   ; combout          ;
; |lab7|heartbeat:u1|Add4~52   ; |lab7|heartbeat:u1|Add4~53   ; cout             ;
; |lab7|heartbeat:u1|Add4~54   ; |lab7|heartbeat:u1|Add4~54   ; combout          ;
; |lab7|heartbeat:u1|d0_reg[3] ; |lab7|heartbeat:u1|d0_reg[3] ; regout           ;
; |lab7|heartbeat:u1|d0_reg[2] ; |lab7|heartbeat:u1|d0_reg[2] ; regout           ;
; |lab7|heartbeat:u1|d1_reg[3] ; |lab7|heartbeat:u1|d1_reg[3] ; regout           ;
; |lab7|heartbeat:u1|d1_reg[2] ; |lab7|heartbeat:u1|d1_reg[2] ; regout           ;
; |lab7|heartbeat:u1|d2_reg[3] ; |lab7|heartbeat:u1|d2_reg[3] ; regout           ;
; |lab7|heartbeat:u1|d2_reg[2] ; |lab7|heartbeat:u1|d2_reg[2] ; regout           ;
; |lab7|heartbeat:u1|d3_reg[3] ; |lab7|heartbeat:u1|d3_reg[3] ; regout           ;
; |lab7|heartbeat:u1|d3_reg[2] ; |lab7|heartbeat:u1|d3_reg[2] ; regout           ;
; |lab7|ssega[0]               ; |lab7|ssega[0]               ; padio            ;
; |lab7|ssega[3]               ; |lab7|ssega[3]               ; padio            ;
; |lab7|ssega[4]               ; |lab7|ssega[4]               ; padio            ;
; |lab7|ssega[5]               ; |lab7|ssega[5]               ; padio            ;
; |lab7|ssega[6]               ; |lab7|ssega[6]               ; padio            ;
; |lab7|ssegb[0]               ; |lab7|ssegb[0]               ; padio            ;
; |lab7|ssegb[3]               ; |lab7|ssegb[3]               ; padio            ;
; |lab7|ssegb[6]               ; |lab7|ssegb[6]               ; padio            ;
; |lab7|ssegc[0]               ; |lab7|ssegc[0]               ; padio            ;
; |lab7|ssegc[3]               ; |lab7|ssegc[3]               ; padio            ;
; |lab7|ssegc[6]               ; |lab7|ssegc[6]               ; padio            ;
; |lab7|ssegd[0]               ; |lab7|ssegd[0]               ; padio            ;
; |lab7|ssegd[1]               ; |lab7|ssegd[1]               ; padio            ;
; |lab7|ssegd[2]               ; |lab7|ssegd[2]               ; padio            ;
; |lab7|ssegd[3]               ; |lab7|ssegd[3]               ; padio            ;
; |lab7|ssegd[6]               ; |lab7|ssegd[6]               ; padio            ;
+------------------------------+------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Web Edition
    Info: Processing started: Tue Oct 21 02:02:31 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off lab7 -c lab7
Info: Using vector source file "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/lab7.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      60.00 %
Info: Number of transitions in simulation is 1652
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 110 megabytes
    Info: Processing ended: Tue Oct 21 02:02:33 2008
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01