prev_cmp_heartbeat.tan.qmsg

用VHDL编译的源代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register ms_reg\[1\] register d0_reg\[2\] 276.01 MHz 3.623 ns Internal " "Info: Clock \"clk\" has Internal fmax of 276.01 MHz between source register \"ms_reg\[1\]\" and destination register \"d0_reg\[2\]\" (period= 3.623 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.386 ns + Longest register register " "Info: + Longest register to register delay is 3.386 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ms_reg\[1\] 1 REG LCFF_X2_Y13_N29 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y13_N29; Fanout = 4; REG Node = 'ms_reg\[1\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ms_reg[1] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.322 ns) 0.948 ns Equal0~52 2 COMB LCCOMB_X2_Y13_N30 6 " "Info: 2: + IC(0.626 ns) + CELL(0.322 ns) = 0.948 ns; Loc. = LCCOMB_X2_Y13_N30; Fanout = 6; COMB Node = 'Equal0~52'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.948 ns" { ms_reg[1] Equal0~52 } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.319 ns) + CELL(0.495 ns) 1.762 ns Add2~49 3 COMB LCCOMB_X2_Y13_N2 2 " "Info: 3: + IC(0.319 ns) + CELL(0.495 ns) = 1.762 ns; Loc. = LCCOMB_X2_Y13_N2; Fanout = 2; COMB Node = 'Add2~49'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.814 ns" { Equal0~52 Add2~49 } "NODE_NAME" } } { "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" "" { Text "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" 1244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.842 ns Add2~51 4 COMB LCCOMB_X2_Y13_N4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.842 ns; Loc. = LCCOMB_X2_Y13_N4; Fanout = 2; COMB Node = 'Add2~51'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add2~49 Add2~51 } "NODE_NAME" } } { "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" "" { Text "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" 1244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 2.300 ns Add2~52 5 COMB LCCOMB_X2_Y13_N6 1 " "Info: 5: + IC(0.000 ns) + CELL(0.458 ns) = 2.300 ns; Loc. = LCCOMB_X2_Y13_N6; Fanout = 1; COMB Node = 'Add2~52'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Add2~51 Add2~52 } "NODE_NAME" } } { "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" "" { Text "c:/altera/80sp1/quartus/libraries/vhdl/ieee/numeric_std.vhd" 1244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.812 ns) + CELL(0.178 ns) 3.290 ns d0_next\[2\]~93 6 COMB LCCOMB_X3_Y13_N24 1 " "Info: 6: + IC(0.812 ns) + CELL(0.178 ns) = 3.290 ns; Loc. = LCCOMB_X3_Y13_N24; Fanout = 1; COMB Node = 'd0_next\[2\]~93'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.990 ns" { Add2~52 d0_next[2]~93 } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 3.386 ns d0_reg\[2\] 7 REG LCFF_X3_Y13_N25 4 " "Info: 7: + IC(0.000 ns) + CELL(0.096 ns) = 3.386 ns; Loc. = LCFF_X3_Y13_N25; Fanout = 4; REG Node = 'd0_reg\[2\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { d0_next[2]~93 d0_reg[2] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns ( 48.11 % ) " "Info: Total cell delay = 1.629 ns ( 48.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.757 ns ( 51.89 % ) " "Info: Total interconnect delay = 1.757 ns ( 51.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.386 ns" { ms_reg[1] Equal0~52 Add2~49 Add2~51 Add2~52 d0_next[2]~93 d0_reg[2] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "3.386 ns" { ms_reg[1] {} Equal0~52 {} Add2~49 {} Add2~51 {} Add2~52 {} d0_next[2]~93 {} d0_reg[2] {} } { 0.000ns 0.626ns 0.319ns 0.000ns 0.000ns 0.812ns 0.000ns } { 0.000ns 0.322ns 0.495ns 0.080ns 0.458ns 0.178ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.002 ns - Smallest " "Info: - Smallest clock skew is 0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.864 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.864 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 13 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.602 ns) 2.864 ns d0_reg\[2\] 3 REG LCFF_X3_Y13_N25 4 " "Info: 3: + IC(0.998 ns) + CELL(0.602 ns) = 2.864 ns; Loc. = LCFF_X3_Y13_N25; Fanout = 4; REG Node = 'd0_reg\[2\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { clk~clkctrl d0_reg[2] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.84 % ) " "Info: Total cell delay = 1.628 ns ( 56.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.236 ns ( 43.16 % ) " "Info: Total interconnect delay = 1.236 ns ( 43.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { clk clk~clkctrl d0_reg[2] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { clk {} clk~combout {} clk~clkctrl {} d0_reg[2] {} } { 0.000ns 0.000ns 0.238ns 0.998ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.862 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 13 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.996 ns) + CELL(0.602 ns) 2.862 ns ms_reg\[1\] 3 REG LCFF_X2_Y13_N29 4 " "Info: 3: + IC(0.996 ns) + CELL(0.602 ns) = 2.862 ns; Loc. = LCFF_X2_Y13_N29; Fanout = 4; REG Node = 'ms_reg\[1\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.598 ns" { clk~clkctrl ms_reg[1] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.88 % ) " "Info: Total cell delay = 1.628 ns ( 56.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.234 ns ( 43.12 % ) " "Info: Total interconnect delay = 1.234 ns ( 43.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.862 ns" { clk clk~clkctrl ms_reg[1] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.862 ns" { clk {} clk~combout {} clk~clkctrl {} ms_reg[1] {} } { 0.000ns 0.000ns 0.238ns 0.996ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { clk clk~clkctrl d0_reg[2] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { clk {} clk~combout {} clk~clkctrl {} d0_reg[2] {} } { 0.000ns 0.000ns 0.238ns 0.998ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.862 ns" { clk clk~clkctrl ms_reg[1] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.862 ns" { clk {} clk~combout {} clk~clkctrl {} ms_reg[1] {} } { 0.000ns 0.000ns 0.238ns 0.996ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.386 ns" { ms_reg[1] Equal0~52 Add2~49 Add2~51 Add2~52 d0_next[2]~93 d0_reg[2] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "3.386 ns" { ms_reg[1] {} Equal0~52 {} Add2~49 {} Add2~51 {} Add2~52 {} d0_next[2]~93 {} d0_reg[2] {} } { 0.000ns 0.626ns 0.319ns 0.000ns 0.000ns 0.812ns 0.000ns } { 0.000ns 0.322ns 0.495ns 0.080ns 0.458ns 0.178ns 0.096ns } "" } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { clk clk~clkctrl d0_reg[2] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { clk {} clk~combout {} clk~clkctrl {} d0_reg[2] {} } { 0.000ns 0.000ns 0.238ns 0.998ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.862 ns" { clk clk~clkctrl ms_reg[1] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.862 ns" { clk {} clk~combout {} clk~clkctrl {} ms_reg[1] {} } { 0.000ns 0.000ns 0.238ns 0.996ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk d0\[1\] d0_reg\[1\] 9.848 ns register " "Info: tco from clock \"clk\" to destination pin \"d0\[1\]\" through register \"d0_reg\[1\]\" is 9.848 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.862 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 13 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 13; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.996 ns) + CELL(0.602 ns) 2.862 ns d0_reg\[1\] 3 REG LCFF_X2_Y13_N5 10 " "Info: 3: + IC(0.996 ns) + CELL(0.602 ns) = 2.862 ns; Loc. = LCFF_X2_Y13_N5; Fanout = 10; REG Node = 'd0_reg\[1\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.598 ns" { clk~clkctrl d0_reg[1] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.88 % ) " "Info: Total cell delay = 1.628 ns ( 56.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.234 ns ( 43.12 % ) " "Info: Total interconnect delay = 1.234 ns ( 43.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.862 ns" { clk clk~clkctrl d0_reg[1] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.862 ns" { clk {} clk~combout {} clk~clkctrl {} d0_reg[1] {} } { 0.000ns 0.000ns 0.238ns 0.996ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.709 ns + Longest register pin " "Info: + Longest register to pin delay is 6.709 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns d0_reg\[1\] 1 REG LCFF_X2_Y13_N5 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y13_N5; Fanout = 10; REG Node = 'd0_reg\[1\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { d0_reg[1] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.889 ns) + CELL(2.820 ns) 6.709 ns d0\[1\] 2 PIN PIN_H16 0 " "Info: 2: + IC(3.889 ns) + CELL(2.820 ns) = 6.709 ns; Loc. = PIN_H16; Fanout = 0; PIN Node = 'd0\[1\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.709 ns" { d0_reg[1] d0[1] } "NODE_NAME" } } { "heartbeat.vhd" "" { Text "H:/EEC 587 Rapid Digital System Prototyping/VHDL/lab7/heartbeat/heartbeat.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.820 ns ( 42.03 % ) " "Info: Total cell delay = 2.820 ns ( 42.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.889 ns ( 57.97 % ) " "Info: Total interconnect delay = 3.889 ns ( 57.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.709 ns" { d0_reg[1] d0[1] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "6.709 ns" { d0_reg[1] {} d0[1] {} } { 0.000ns 3.889ns } { 0.000ns 2.820ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.862 ns" { clk clk~clkctrl d0_reg[1] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.862 ns" { clk {} clk~combout {} clk~clkctrl {} d0_reg[1] {} } { 0.000ns 0.000ns 0.238ns 0.996ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.709 ns" { d0_reg[1] d0[1] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "6.709 ns" { d0_reg[1] {} d0[1] {} } { 0.000ns 3.889ns } { 0.000ns 2.820ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "123 " "Info: Peak virtual memory: 123 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 21 02:16:25 2008 " "Info: Processing ended: Tue Oct 21 02:16:25 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}