ppg.qsf

用VHDL编译的源代码

# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		ppg_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20F484C7
set_global_assignment -name TOP_LEVEL_ENTITY ppg
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "8.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:45:45  SEPTEMBER 29, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 8.0
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_L1 -to clk
set_location_assignment PIN_L22 -to d[0]
set_location_assignment PIN_L21 -to d[1]
set_location_assignment PIN_M22 -to d[2]
set_location_assignment PIN_V12 -to d[3]
set_location_assignment PIN_W12 -to w[0]
set_location_assignment PIN_U12 -to w[1]
set_location_assignment PIN_U11 -to w[2]
set_location_assignment PIN_M2 -to w[3]
set_location_assignment PIN_M1 -to reset
set_location_assignment PIN_A13 -to pwm_pulse
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
set_global_assignment -name VHDL_FILE ppg.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE ppg.vwf