pwm.tan.qmsg

用VHDL编译的源代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register r_reg\[0\] buf_reg 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"r_reg\[0\]\" and destination register \"buf_reg\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.459 ns + Longest register register " "Info: + Longest register to register delay is 1.459 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns r_reg\[0\] 1 REG LCFF_X31_Y35_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y35_N9; Fanout = 5; REG Node = 'r_reg\[0\]'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_reg[0] } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.314 ns) + CELL(0.275 ns) 0.589 ns buf_next~258 2 COMB LCCOMB_X31_Y35_N28 1 " "Info: 2: + IC(0.314 ns) + CELL(0.275 ns) = 0.589 ns; Loc. = LCCOMB_X31_Y35_N28; Fanout = 1; COMB Node = 'buf_next~258'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.589 ns" { r_reg[0] buf_next~258 } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.242 ns) + CELL(0.150 ns) 0.981 ns buf_next~259 3 COMB LCCOMB_X31_Y35_N30 1 " "Info: 3: + IC(0.242 ns) + CELL(0.150 ns) = 0.981 ns; Loc. = LCCOMB_X31_Y35_N30; Fanout = 1; COMB Node = 'buf_next~259'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.392 ns" { buf_next~258 buf_next~259 } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.244 ns) + CELL(0.150 ns) 1.375 ns buf_next~260 4 COMB LCCOMB_X31_Y35_N0 1 " "Info: 4: + IC(0.244 ns) + CELL(0.150 ns) = 1.375 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'buf_next~260'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { buf_next~259 buf_next~260 } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.459 ns buf_reg 5 REG LCFF_X31_Y35_N1 1 " "Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 1.459 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'buf_reg'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { buf_next~260 buf_reg } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.659 ns ( 45.17 % ) " "Info: Total cell delay = 0.659 ns ( 45.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns ( 54.83 % ) " "Info: Total interconnect delay = 0.800 ns ( 54.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.459 ns" { r_reg[0] buf_next~258 buf_next~259 buf_next~260 buf_reg } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "1.459 ns" { r_reg[0] {} buf_next~258 {} buf_next~259 {} buf_next~260 {} buf_reg {} } { 0.000ns 0.314ns 0.242ns 0.244ns 0.000ns } { 0.000ns 0.275ns 0.150ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.698 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 5 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.537 ns) 2.698 ns buf_reg 3 REG LCFF_X31_Y35_N1 1 " "Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'buf_reg'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.581 ns" { clk~clkctrl buf_reg } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.93 % ) " "Info: Total cell delay = 1.536 ns ( 56.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns ( 43.07 % ) " "Info: Total interconnect delay = 1.162 ns ( 43.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl buf_reg } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { clk {} clk~combout {} clk~clkctrl {} buf_reg {} } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.698 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 5 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.537 ns) 2.698 ns r_reg\[0\] 3 REG LCFF_X31_Y35_N9 5 " "Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X31_Y35_N9; Fanout = 5; REG Node = 'r_reg\[0\]'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.581 ns" { clk~clkctrl r_reg[0] } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.93 % ) " "Info: Total cell delay = 1.536 ns ( 56.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns ( 43.07 % ) " "Info: Total interconnect delay = 1.162 ns ( 43.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl r_reg[0] } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { clk {} clk~combout {} clk~clkctrl {} r_reg[0] {} } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl buf_reg } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { clk {} clk~combout {} clk~clkctrl {} buf_reg {} } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl r_reg[0] } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { clk {} clk~combout {} clk~clkctrl {} r_reg[0] {} } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.459 ns" { r_reg[0] buf_next~258 buf_next~259 buf_next~260 buf_reg } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "1.459 ns" { r_reg[0] {} buf_next~258 {} buf_next~259 {} buf_next~260 {} buf_reg {} } { 0.000ns 0.314ns 0.242ns 0.244ns 0.000ns } { 0.000ns 0.275ns 0.150ns 0.150ns 0.084ns } "" } } { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl buf_reg } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { clk {} clk~combout {} clk~clkctrl {} buf_reg {} } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl r_reg[0] } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { clk {} clk~combout {} clk~clkctrl {} r_reg[0] {} } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { buf_reg } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { buf_reg {} } {  } {  } "" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 20 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "buf_reg w\[3\] clk 5.799 ns register " "Info: tsu for register \"buf_reg\" (data pin = \"w\[3\]\", clock pin = \"clk\") is 5.799 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.533 ns + Longest pin register " "Info: + Longest pin to register delay is 8.533 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns w\[3\] 1 PIN PIN_AD12 2 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_AD12; Fanout = 2; PIN Node = 'w\[3\]'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { w[3] } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.514 ns) + CELL(0.398 ns) 7.762 ns Equal0~28 2 COMB LCCOMB_X31_Y35_N26 1 " "Info: 2: + IC(6.514 ns) + CELL(0.398 ns) = 7.762 ns; Loc. = LCCOMB_X31_Y35_N26; Fanout = 1; COMB Node = 'Equal0~28'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.912 ns" { w[3] Equal0~28 } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.245 ns) 8.449 ns buf_next~260 3 COMB LCCOMB_X31_Y35_N0 1 " "Info: 3: + IC(0.442 ns) + CELL(0.245 ns) = 8.449 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'buf_next~260'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.687 ns" { Equal0~28 buf_next~260 } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 8.533 ns buf_reg 4 REG LCFF_X31_Y35_N1 1 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 8.533 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'buf_reg'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { buf_next~260 buf_reg } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.577 ns ( 18.48 % ) " "Info: Total cell delay = 1.577 ns ( 18.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.956 ns ( 81.52 % ) " "Info: Total interconnect delay = 6.956 ns ( 81.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "8.533 ns" { w[3] Equal0~28 buf_next~260 buf_reg } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "8.533 ns" { w[3] {} w[3]~combout {} Equal0~28 {} buf_next~260 {} buf_reg {} } { 0.000ns 0.000ns 6.514ns 0.442ns 0.000ns } { 0.000ns 0.850ns 0.398ns 0.245ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.698 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 5 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.537 ns) 2.698 ns buf_reg 3 REG LCFF_X31_Y35_N1 1 " "Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'buf_reg'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.581 ns" { clk~clkctrl buf_reg } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.93 % ) " "Info: Total cell delay = 1.536 ns ( 56.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns ( 43.07 % ) " "Info: Total interconnect delay = 1.162 ns ( 43.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl buf_reg } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { clk {} clk~combout {} clk~clkctrl {} buf_reg {} } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "8.533 ns" { w[3] Equal0~28 buf_next~260 buf_reg } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "8.533 ns" { w[3] {} w[3]~combout {} Equal0~28 {} buf_next~260 {} buf_reg {} } { 0.000ns 0.000ns 6.514ns 0.442ns 0.000ns } { 0.000ns 0.850ns 0.398ns 0.245ns 0.084ns } "" } } { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl buf_reg } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { clk {} clk~combout {} clk~clkctrl {} buf_reg {} } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk pwm_pulse buf_reg 6.603 ns register " "Info: tco from clock \"clk\" to destination pin \"pwm_pulse\" through register \"buf_reg\" is 6.603 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.698 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 5 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.537 ns) 2.698 ns buf_reg 3 REG LCFF_X31_Y35_N1 1 " "Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'buf_reg'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.581 ns" { clk~clkctrl buf_reg } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.93 % ) " "Info: Total cell delay = 1.536 ns ( 56.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns ( 43.07 % ) " "Info: Total interconnect delay = 1.162 ns ( 43.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl buf_reg } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { clk {} clk~combout {} clk~clkctrl {} buf_reg {} } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.655 ns + Longest register pin " "Info: + Longest register to pin delay is 3.655 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns buf_reg 1 REG LCFF_X31_Y35_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'buf_reg'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { buf_reg } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.857 ns) + CELL(2.798 ns) 3.655 ns pwm_pulse 2 PIN PIN_B14 0 " "Info: 2: + IC(0.857 ns) + CELL(2.798 ns) = 3.655 ns; Loc. = PIN_B14; Fanout = 0; PIN Node = 'pwm_pulse'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.655 ns" { buf_reg pwm_pulse } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.798 ns ( 76.55 % ) " "Info: Total cell delay = 2.798 ns ( 76.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.857 ns ( 23.45 % ) " "Info: Total interconnect delay = 0.857 ns ( 23.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.655 ns" { buf_reg pwm_pulse } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "3.655 ns" { buf_reg {} pwm_pulse {} } { 0.000ns 0.857ns } { 0.000ns 2.798ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl buf_reg } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { clk {} clk~combout {} clk~clkctrl {} buf_reg {} } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.655 ns" { buf_reg pwm_pulse } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "3.655 ns" { buf_reg {} pwm_pulse {} } { 0.000ns 0.857ns } { 0.000ns 2.798ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "buf_reg w\[0\] clk 0.293 ns register " "Info: th for register \"buf_reg\" (data pin = \"w\[0\]\", clock pin = \"clk\") is 0.293 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.698 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 5 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.537 ns) 2.698 ns buf_reg 3 REG LCFF_X31_Y35_N1 1 " "Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'buf_reg'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.581 ns" { clk~clkctrl buf_reg } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.93 % ) " "Info: Total cell delay = 1.536 ns ( 56.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns ( 43.07 % ) " "Info: Total interconnect delay = 1.162 ns ( 43.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl buf_reg } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { clk {} clk~combout {} clk~clkctrl {} buf_reg {} } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.671 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.671 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns w\[0\] 1 PIN PIN_D13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 2; PIN Node = 'w\[0\]'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { w[0] } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.275 ns) 1.900 ns Equal0~28 2 COMB LCCOMB_X31_Y35_N26 1 " "Info: 2: + IC(0.646 ns) + CELL(0.275 ns) = 1.900 ns; Loc. = LCCOMB_X31_Y35_N26; Fanout = 1; COMB Node = 'Equal0~28'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.921 ns" { w[0] Equal0~28 } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.245 ns) 2.587 ns buf_next~260 3 COMB LCCOMB_X31_Y35_N0 1 " "Info: 3: + IC(0.442 ns) + CELL(0.245 ns) = 2.587 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'buf_next~260'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.687 ns" { Equal0~28 buf_next~260 } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.671 ns buf_reg 4 REG LCFF_X31_Y35_N1 1 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 2.671 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'buf_reg'" {  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { buf_next~260 buf_reg } "NODE_NAME" } } { "pwm.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EEC 587/VHDL/pwm/pwm.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.583 ns ( 59.27 % ) " "Info: Total cell delay = 1.583 ns ( 59.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.088 ns ( 40.73 % ) " "Info: Total interconnect delay = 1.088 ns ( 40.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.671 ns" { w[0] Equal0~28 buf_next~260 buf_reg } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.671 ns" { w[0] {} w[0]~combout {} Equal0~28 {} buf_next~260 {} buf_reg {} } { 0.000ns 0.000ns 0.646ns 0.442ns 0.000ns } { 0.000ns 0.979ns 0.275ns 0.245ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { clk clk~clkctrl buf_reg } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { clk {} clk~combout {} clk~clkctrl {} buf_reg {} } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.671 ns" { w[0] Equal0~28 buf_next~260 buf_reg } "NODE_NAME" } } { "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.671 ns" { w[0] {} w[0]~combout {} Equal0~28 {} buf_next~260 {} buf_reg {} } { 0.000ns 0.000ns 0.646ns 0.442ns 0.000ns } { 0.000ns 0.979ns 0.275ns 0.245ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}