pwm.tan.rpt

用VHDL编译的源代码

; Slack ; Required tsu ; Actual tsu ; From ; To      ; To Clock ;
+-------+--------------+------------+------+---------+----------+
; N/A   ; None         ; 5.799 ns   ; w[3] ; buf_reg ; clk      ;
; N/A   ; None         ; 4.570 ns   ; w[2] ; buf_reg ; clk      ;
; N/A   ; None         ; 0.211 ns   ; w[0] ; buf_reg ; clk      ;
; N/A   ; None         ; 0.181 ns   ; w[1] ; buf_reg ; clk      ;
+-------+--------------+------------+------+---------+----------+


+----------------------------------------------------------------------+
; tco                                                                  ;
+-------+--------------+------------+---------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From    ; To        ; From Clock ;
+-------+--------------+------------+---------+-----------+------------+
; N/A   ; None         ; 6.603 ns   ; buf_reg ; pwm_pulse ; clk        ;
+-------+--------------+------------+---------+-----------+------------+


+---------------------------------------------------------------------+
; th                                                                  ;
+---------------+-------------+-----------+------+---------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To      ; To Clock ;
+---------------+-------------+-----------+------+---------+----------+
; N/A           ; None        ; 0.293 ns  ; w[0] ; buf_reg ; clk      ;
; N/A           ; None        ; 0.197 ns  ; w[1] ; buf_reg ; clk      ;
; N/A           ; None        ; -4.317 ns ; w[2] ; buf_reg ; clk      ;
; N/A           ; None        ; -4.918 ns ; w[3] ; buf_reg ; clk      ;
+---------------+-------------+-----------+------+---------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Web Edition
    Info: Processing started: Mon Sep 29 23:35:22 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off pwm -c pwm --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "r_reg[0]" and destination register "buf_reg"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.459 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y35_N9; Fanout = 5; REG Node = 'r_reg[0]'
            Info: 2: + IC(0.314 ns) + CELL(0.275 ns) = 0.589 ns; Loc. = LCCOMB_X31_Y35_N28; Fanout = 1; COMB Node = 'buf_next~258'
            Info: 3: + IC(0.242 ns) + CELL(0.150 ns) = 0.981 ns; Loc. = LCCOMB_X31_Y35_N30; Fanout = 1; COMB Node = 'buf_next~259'
            Info: 4: + IC(0.244 ns) + CELL(0.150 ns) = 1.375 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'buf_next~260'
            Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 1.459 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'buf_reg'
            Info: Total cell delay = 0.659 ns ( 45.17 % )
            Info: Total interconnect delay = 0.800 ns ( 54.83 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.698 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'buf_reg'
                Info: Total cell delay = 1.536 ns ( 56.93 % )
                Info: Total interconnect delay = 1.162 ns ( 43.07 % )
            Info: - Longest clock path from clock "clk" to source register is 2.698 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X31_Y35_N9; Fanout = 5; REG Node = 'r_reg[0]'
                Info: Total cell delay = 1.536 ns ( 56.93 % )
                Info: Total interconnect delay = 1.162 ns ( 43.07 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "buf_reg" (data pin = "w[3]", clock pin = "clk") is 5.799 ns
    Info: + Longest pin to register delay is 8.533 ns
        Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_AD12; Fanout = 2; PIN Node = 'w[3]'
        Info: 2: + IC(6.514 ns) + CELL(0.398 ns) = 7.762 ns; Loc. = LCCOMB_X31_Y35_N26; Fanout = 1; COMB Node = 'Equal0~28'
        Info: 3: + IC(0.442 ns) + CELL(0.245 ns) = 8.449 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'buf_next~260'
        Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 8.533 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'buf_reg'
        Info: Total cell delay = 1.577 ns ( 18.48 % )
        Info: Total interconnect delay = 6.956 ns ( 81.52 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.698 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'buf_reg'
        Info: Total cell delay = 1.536 ns ( 56.93 % )
        Info: Total interconnect delay = 1.162 ns ( 43.07 % )
Info: tco from clock "clk" to destination pin "pwm_pulse" through register "buf_reg" is 6.603 ns
    Info: + Longest clock path from clock "clk" to source register is 2.698 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'buf_reg'
        Info: Total cell delay = 1.536 ns ( 56.93 % )
        Info: Total interconnect delay = 1.162 ns ( 43.07 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.655 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'buf_reg'
        Info: 2: + IC(0.857 ns) + CELL(2.798 ns) = 3.655 ns; Loc. = PIN_B14; Fanout = 0; PIN Node = 'pwm_pulse'
        Info: Total cell delay = 2.798 ns ( 76.55 % )
        Info: Total interconnect delay = 0.857 ns ( 23.45 % )
Info: th for register "buf_reg" (data pin = "w[0]", clock pin = "clk") is 0.293 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.698 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'buf_reg'
        Info: Total cell delay = 1.536 ns ( 56.93 % )
        Info: Total interconnect delay = 1.162 ns ( 43.07 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 2.671 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 2; PIN Node = 'w[0]'
        Info: 2: + IC(0.646 ns) + CELL(0.275 ns) = 1.900 ns; Loc. = LCCOMB_X31_Y35_N26; Fanout = 1; COMB Node = 'Equal0~28'
        Info: 3: + IC(0.442 ns) + CELL(0.245 ns) = 2.587 ns; Loc. = LCCOMB_X31_Y35_N0; Fanout = 1; COMB Node = 'buf_next~260'
        Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 2.671 ns; Loc. = LCFF_X31_Y35_N1; Fanout = 1; REG Node = 'buf_reg'
        Info: Total cell delay = 1.583 ns ( 59.27 % )
        Info: Total interconnect delay = 1.088 ns ( 40.73 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 124 megabytes
    Info: Processing ended: Mon Sep 29 23:35:23 2008
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01