ppg.hier_info

用VHDL编译的源代码

|ppg
clk => r_reg[4].CLK
clk => r_reg[3].CLK
clk => r_reg[2].CLK
clk => r_reg[1].CLK
clk => r_reg[0].CLK
clk => buf_reg.CLK
reset => r_reg[4].ACLR
reset => r_reg[3].ACLR
reset => r_reg[2].ACLR
reset => r_reg[1].ACLR
reset => r_reg[0].ACLR
reset => buf_reg.ACLR
w[0] => Add1.IN4
w[1] => Add1.IN3
w[2] => Add1.IN2
w[3] => Add1.IN1
d[0] => LessThan2.IN5
d[0] => LessThan0.IN5
d[0] => Add1.IN8
d[1] => LessThan2.IN4
d[1] => LessThan0.IN4
d[1] => Add1.IN7
d[2] => LessThan2.IN3
d[2] => LessThan0.IN3
d[2] => Add1.IN6
d[3] => LessThan2.IN2
d[3] => LessThan0.IN2
d[3] => Add1.IN5
pwm_pulse <= buf_reg.DB_MAX_OUTPUT_PORT_TYPE