ppg.tan.qmsg

用VHDL编译的源代码

{ "Info" "ITDB_TH_RESULT" "r_reg\[3\] d\[2\] clk -1.451 ns register " "Info: th for register \"r_reg\[3\]\" (data pin = \"d\[2\]\", clock pin = \"clk\") is -1.451 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.868 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.868 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.002 ns) + CELL(0.602 ns) 2.868 ns r_reg\[3\] 3 REG LCFF_X43_Y13_N21 7 " "Info: 3: + IC(1.002 ns) + CELL(0.602 ns) = 2.868 ns; Loc. = LCFF_X43_Y13_N21; Fanout = 7; REG Node = 'r_reg\[3\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "1.604 ns" { clk~clkctrl r_reg[3] } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.76 % ) " "Info: Total cell delay = 1.628 ns ( 56.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.240 ns ( 43.24 % ) " "Info: Total interconnect delay = 1.240 ns ( 43.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl r_reg[3] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} r_reg[3] {} } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.605 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.605 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns d\[2\] 1 PIN PIN_M22 6 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_M22; Fanout = 6; PIN Node = 'd\[2\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "" { d[2] } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.151 ns) + CELL(0.544 ns) 2.731 ns Add1~64 2 COMB LCCOMB_X42_Y13_N22 2 " "Info: 2: + IC(1.151 ns) + CELL(0.544 ns) = 2.731 ns; Loc. = LCCOMB_X42_Y13_N22; Fanout = 2; COMB Node = 'Add1~64'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "1.695 ns" { d[2] Add1~64 } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.532 ns) + CELL(0.491 ns) 3.754 ns Equal0~32 3 COMB LCCOMB_X43_Y13_N6 5 " "Info: 3: + IC(0.532 ns) + CELL(0.491 ns) = 3.754 ns; Loc. = LCCOMB_X43_Y13_N6; Fanout = 5; COMB Node = 'Equal0~32'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "1.023 ns" { Add1~64 Equal0~32 } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.271 ns) + CELL(0.580 ns) 4.605 ns r_reg\[3\] 4 REG LCFF_X43_Y13_N21 7 " "Info: 4: + IC(0.271 ns) + CELL(0.580 ns) = 4.605 ns; Loc. = LCFF_X43_Y13_N21; Fanout = 7; REG Node = 'r_reg\[3\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.851 ns" { Equal0~32 r_reg[3] } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.651 ns ( 57.57 % ) " "Info: Total cell delay = 2.651 ns ( 57.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.954 ns ( 42.43 % ) " "Info: Total interconnect delay = 1.954 ns ( 42.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "4.605 ns" { d[2] Add1~64 Equal0~32 r_reg[3] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "4.605 ns" { d[2] {} d[2]~combout {} Add1~64 {} Equal0~32 {} r_reg[3] {} } { 0.000ns 0.000ns 1.151ns 0.532ns 0.271ns } { 0.000ns 1.036ns 0.544ns 0.491ns 0.580ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl r_reg[3] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} r_reg[3] {} } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "4.605 ns" { d[2] Add1~64 Equal0~32 r_reg[3] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "4.605 ns" { d[2] {} d[2]~combout {} Add1~64 {} Equal0~32 {} r_reg[3] {} } { 0.000ns 0.000ns 1.151ns 0.532ns 0.271ns } { 0.000ns 1.036ns 0.544ns 0.491ns 0.580ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "127 " "Info: Peak virtual memory: 127 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 14 14:38:14 2008 " "Info: Processing ended: Tue Oct 14 14:38:14 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}