ppg.tan.qmsg

用VHDL编译的源代码

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 6 -1 0 } } { "c:/eda/altera/v80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/eda/altera/v80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register r_reg\[0\] r_reg\[3\] 380.08 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 380.08 MHz between source register \"r_reg\[0\]\" and destination register \"r_reg\[3\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.631 ns " "Info: fmax restricted to clock pin edge rate 2.631 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.204 ns + Longest register register " "Info: + Longest register to register delay is 2.204 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns r_reg\[0\] 1 REG LCFF_X43_Y13_N15 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X43_Y13_N15; Fanout = 6; REG Node = 'r_reg\[0\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_reg[0] } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.557 ns) + CELL(0.178 ns) 0.735 ns Equal0~31 2 COMB LCCOMB_X43_Y13_N4 1 " "Info: 2: + IC(0.557 ns) + CELL(0.178 ns) = 0.735 ns; Loc. = LCCOMB_X43_Y13_N4; Fanout = 1; COMB Node = 'Equal0~31'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.735 ns" { r_reg[0] Equal0~31 } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.296 ns) + CELL(0.322 ns) 1.353 ns Equal0~32 3 COMB LCCOMB_X43_Y13_N6 5 " "Info: 3: + IC(0.296 ns) + CELL(0.322 ns) = 1.353 ns; Loc. = LCCOMB_X43_Y13_N6; Fanout = 5; COMB Node = 'Equal0~32'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.618 ns" { Equal0~31 Equal0~32 } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.271 ns) + CELL(0.580 ns) 2.204 ns r_reg\[3\] 4 REG LCFF_X43_Y13_N21 7 " "Info: 4: + IC(0.271 ns) + CELL(0.580 ns) = 2.204 ns; Loc. = LCFF_X43_Y13_N21; Fanout = 7; REG Node = 'r_reg\[3\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.851 ns" { Equal0~32 r_reg[3] } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.080 ns ( 49.00 % ) " "Info: Total cell delay = 1.080 ns ( 49.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.124 ns ( 51.00 % ) " "Info: Total interconnect delay = 1.124 ns ( 51.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.204 ns" { r_reg[0] Equal0~31 Equal0~32 r_reg[3] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.204 ns" { r_reg[0] {} Equal0~31 {} Equal0~32 {} r_reg[3] {} } { 0.000ns 0.557ns 0.296ns 0.271ns } { 0.000ns 0.178ns 0.322ns 0.580ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.868 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.868 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.002 ns) + CELL(0.602 ns) 2.868 ns r_reg\[3\] 3 REG LCFF_X43_Y13_N21 7 " "Info: 3: + IC(1.002 ns) + CELL(0.602 ns) = 2.868 ns; Loc. = LCFF_X43_Y13_N21; Fanout = 7; REG Node = 'r_reg\[3\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "1.604 ns" { clk~clkctrl r_reg[3] } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.76 % ) " "Info: Total cell delay = 1.628 ns ( 56.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.240 ns ( 43.24 % ) " "Info: Total interconnect delay = 1.240 ns ( 43.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl r_reg[3] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} r_reg[3] {} } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.868 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.868 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.002 ns) + CELL(0.602 ns) 2.868 ns r_reg\[0\] 3 REG LCFF_X43_Y13_N15 6 " "Info: 3: + IC(1.002 ns) + CELL(0.602 ns) = 2.868 ns; Loc. = LCFF_X43_Y13_N15; Fanout = 6; REG Node = 'r_reg\[0\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "1.604 ns" { clk~clkctrl r_reg[0] } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.76 % ) " "Info: Total cell delay = 1.628 ns ( 56.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.240 ns ( 43.24 % ) " "Info: Total interconnect delay = 1.240 ns ( 43.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl r_reg[0] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} r_reg[0] {} } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl r_reg[3] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} r_reg[3] {} } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl r_reg[0] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} r_reg[0] {} } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.204 ns" { r_reg[0] Equal0~31 Equal0~32 r_reg[3] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.204 ns" { r_reg[0] {} Equal0~31 {} Equal0~32 {} r_reg[3] {} } { 0.000ns 0.557ns 0.296ns 0.271ns } { 0.000ns 0.178ns 0.322ns 0.580ns } "" } } { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl r_reg[3] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} r_reg[3] {} } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl r_reg[0] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} r_reg[0] {} } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_reg[3] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { r_reg[3] {} } {  } {  } "" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 20 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "r_reg\[3\] w\[1\] clk 4.176 ns register " "Info: tsu for register \"r_reg\[3\]\" (data pin = \"w\[1\]\", clock pin = \"clk\") is 4.176 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.082 ns + Longest pin register " "Info: + Longest pin to register delay is 7.082 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.006 ns) 1.006 ns w\[1\] 1 PIN PIN_U12 2 " "Info: 1: + IC(0.000 ns) + CELL(1.006 ns) = 1.006 ns; Loc. = PIN_U12; Fanout = 2; PIN Node = 'w\[1\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "" { w[1] } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.275 ns) + CELL(0.517 ns) 3.798 ns Add1~63 2 COMB LCCOMB_X42_Y13_N20 2 " "Info: 2: + IC(2.275 ns) + CELL(0.517 ns) = 3.798 ns; Loc. = LCCOMB_X42_Y13_N20; Fanout = 2; COMB Node = 'Add1~63'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.792 ns" { w[1] Add1~63 } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 3.878 ns Add1~65 3 COMB LCCOMB_X42_Y13_N22 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 3.878 ns; Loc. = LCCOMB_X42_Y13_N22; Fanout = 2; COMB Node = 'Add1~65'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~63 Add1~65 } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 3.958 ns Add1~67 4 COMB LCCOMB_X42_Y13_N24 1 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 3.958 ns; Loc. = LCCOMB_X42_Y13_N24; Fanout = 1; COMB Node = 'Add1~67'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add1~65 Add1~67 } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 4.416 ns Add1~68 5 COMB LCCOMB_X42_Y13_N26 2 " "Info: 5: + IC(0.000 ns) + CELL(0.458 ns) = 4.416 ns; Loc. = LCCOMB_X42_Y13_N26; Fanout = 2; COMB Node = 'Add1~68'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Add1~67 Add1~68 } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.826 ns) + CELL(0.512 ns) 5.754 ns LessThan1~249 6 COMB LCCOMB_X43_Y13_N26 2 " "Info: 6: + IC(0.826 ns) + CELL(0.512 ns) = 5.754 ns; Loc. = LCCOMB_X43_Y13_N26; Fanout = 2; COMB Node = 'LessThan1~249'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "1.338 ns" { Add1~68 LessThan1~249 } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.299 ns) + CELL(0.178 ns) 6.231 ns Equal0~32 7 COMB LCCOMB_X43_Y13_N6 5 " "Info: 7: + IC(0.299 ns) + CELL(0.178 ns) = 6.231 ns; Loc. = LCCOMB_X43_Y13_N6; Fanout = 5; COMB Node = 'Equal0~32'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.477 ns" { LessThan1~249 Equal0~32 } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.271 ns) + CELL(0.580 ns) 7.082 ns r_reg\[3\] 8 REG LCFF_X43_Y13_N21 7 " "Info: 8: + IC(0.271 ns) + CELL(0.580 ns) = 7.082 ns; Loc. = LCFF_X43_Y13_N21; Fanout = 7; REG Node = 'r_reg\[3\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.851 ns" { Equal0~32 r_reg[3] } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.411 ns ( 48.16 % ) " "Info: Total cell delay = 3.411 ns ( 48.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.671 ns ( 51.84 % ) " "Info: Total interconnect delay = 3.671 ns ( 51.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "7.082 ns" { w[1] Add1~63 Add1~65 Add1~67 Add1~68 LessThan1~249 Equal0~32 r_reg[3] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "7.082 ns" { w[1] {} w[1]~combout {} Add1~63 {} Add1~65 {} Add1~67 {} Add1~68 {} LessThan1~249 {} Equal0~32 {} r_reg[3] {} } { 0.000ns 0.000ns 2.275ns 0.000ns 0.000ns 0.000ns 0.826ns 0.299ns 0.271ns } { 0.000ns 1.006ns 0.517ns 0.080ns 0.080ns 0.458ns 0.512ns 0.178ns 0.580ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.868 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.868 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.002 ns) + CELL(0.602 ns) 2.868 ns r_reg\[3\] 3 REG LCFF_X43_Y13_N21 7 " "Info: 3: + IC(1.002 ns) + CELL(0.602 ns) = 2.868 ns; Loc. = LCFF_X43_Y13_N21; Fanout = 7; REG Node = 'r_reg\[3\]'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "1.604 ns" { clk~clkctrl r_reg[3] } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.76 % ) " "Info: Total cell delay = 1.628 ns ( 56.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.240 ns ( 43.24 % ) " "Info: Total interconnect delay = 1.240 ns ( 43.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl r_reg[3] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} r_reg[3] {} } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "7.082 ns" { w[1] Add1~63 Add1~65 Add1~67 Add1~68 LessThan1~249 Equal0~32 r_reg[3] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "7.082 ns" { w[1] {} w[1]~combout {} Add1~63 {} Add1~65 {} Add1~67 {} Add1~68 {} LessThan1~249 {} Equal0~32 {} r_reg[3] {} } { 0.000ns 0.000ns 2.275ns 0.000ns 0.000ns 0.000ns 0.826ns 0.299ns 0.271ns } { 0.000ns 1.006ns 0.517ns 0.080ns 0.080ns 0.458ns 0.512ns 0.178ns 0.580ns } "" } } { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl r_reg[3] } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { clk {} clk~combout {} clk~clkctrl {} r_reg[3] {} } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk pwm_pulse buf_reg 9.148 ns register " "Info: tco from clock \"clk\" to destination pin \"pwm_pulse\" through register \"buf_reg\" is 9.148 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.867 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.867 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.602 ns) 2.867 ns buf_reg 3 REG LCFF_X42_Y13_N1 1 " "Info: 3: + IC(1.001 ns) + CELL(0.602 ns) = 2.867 ns; Loc. = LCFF_X42_Y13_N1; Fanout = 1; REG Node = 'buf_reg'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "1.603 ns" { clk~clkctrl buf_reg } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.78 % ) " "Info: Total cell delay = 1.628 ns ( 56.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.239 ns ( 43.22 % ) " "Info: Total interconnect delay = 1.239 ns ( 43.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.867 ns" { clk clk~clkctrl buf_reg } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.867 ns" { clk {} clk~combout {} clk~clkctrl {} buf_reg {} } { 0.000ns 0.000ns 0.238ns 1.001ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.004 ns + Longest register pin " "Info: + Longest register to pin delay is 6.004 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns buf_reg 1 REG LCFF_X42_Y13_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X42_Y13_N1; Fanout = 1; REG Node = 'buf_reg'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "" { buf_reg } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.998 ns) + CELL(3.006 ns) 6.004 ns pwm_pulse 2 PIN PIN_A13 0 " "Info: 2: + IC(2.998 ns) + CELL(3.006 ns) = 6.004 ns; Loc. = PIN_A13; Fanout = 0; PIN Node = 'pwm_pulse'" {  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "6.004 ns" { buf_reg pwm_pulse } "NODE_NAME" } } { "ppg.vhd" "" { Text "G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.006 ns ( 50.07 % ) " "Info: Total cell delay = 3.006 ns ( 50.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.998 ns ( 49.93 % ) " "Info: Total interconnect delay = 2.998 ns ( 49.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "6.004 ns" { buf_reg pwm_pulse } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "6.004 ns" { buf_reg {} pwm_pulse {} } { 0.000ns 2.998ns } { 0.000ns 3.006ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "2.867 ns" { clk clk~clkctrl buf_reg } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "2.867 ns" { clk {} clk~combout {} clk~clkctrl {} buf_reg {} } { 0.000ns 0.000ns 0.238ns 1.001ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/v80/quartus/bin/TimingClosureFloorplan.fld" "" "6.004 ns" { buf_reg pwm_pulse } "NODE_NAME" } } { "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/eda/altera/v80/quartus/bin/Technology_Viewer.qrui" "6.004 ns" { buf_reg {} pwm_pulse {} } { 0.000ns 2.998ns } { 0.000ns 3.006ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}