ppg.tan.rpt

用VHDL编译的源代码

; N/A   ; None         ; 3.079 ns   ; d[1] ; r_reg[1] ; clk      ;
; N/A   ; None         ; 3.079 ns   ; d[1] ; r_reg[0] ; clk      ;
; N/A   ; None         ; 3.079 ns   ; d[1] ; r_reg[4] ; clk      ;
; N/A   ; None         ; 3.002 ns   ; d[2] ; r_reg[3] ; clk      ;
; N/A   ; None         ; 3.002 ns   ; d[2] ; r_reg[2] ; clk      ;
; N/A   ; None         ; 3.002 ns   ; d[2] ; r_reg[1] ; clk      ;
; N/A   ; None         ; 3.002 ns   ; d[2] ; r_reg[0] ; clk      ;
; N/A   ; None         ; 3.002 ns   ; d[2] ; r_reg[4] ; clk      ;
+-------+--------------+------------+------+----------+----------+


+----------------------------------------------------------------------+
; tco                                                                  ;
+-------+--------------+------------+---------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From    ; To        ; From Clock ;
+-------+--------------+------------+---------+-----------+------------+
; N/A   ; None         ; 9.148 ns   ; buf_reg ; pwm_pulse ; clk        ;
+-------+--------------+------------+---------+-----------+------------+


+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To       ; To Clock ;
+---------------+-------------+-----------+------+----------+----------+
; N/A           ; None        ; -1.451 ns ; d[2] ; r_reg[3] ; clk      ;
; N/A           ; None        ; -1.451 ns ; d[2] ; r_reg[2] ; clk      ;
; N/A           ; None        ; -1.451 ns ; d[2] ; r_reg[1] ; clk      ;
; N/A           ; None        ; -1.451 ns ; d[2] ; r_reg[0] ; clk      ;
; N/A           ; None        ; -1.451 ns ; d[2] ; r_reg[4] ; clk      ;
; N/A           ; None        ; -1.879 ns ; d[1] ; r_reg[3] ; clk      ;
; N/A           ; None        ; -1.879 ns ; d[1] ; r_reg[2] ; clk      ;
; N/A           ; None        ; -1.879 ns ; d[1] ; r_reg[1] ; clk      ;
; N/A           ; None        ; -1.879 ns ; d[1] ; r_reg[0] ; clk      ;
; N/A           ; None        ; -1.879 ns ; d[1] ; r_reg[4] ; clk      ;
; N/A           ; None        ; -1.986 ns ; d[0] ; r_reg[3] ; clk      ;
; N/A           ; None        ; -1.986 ns ; d[0] ; r_reg[2] ; clk      ;
; N/A           ; None        ; -1.986 ns ; d[0] ; r_reg[1] ; clk      ;
; N/A           ; None        ; -1.986 ns ; d[0] ; r_reg[0] ; clk      ;
; N/A           ; None        ; -1.986 ns ; d[0] ; r_reg[4] ; clk      ;
; N/A           ; None        ; -2.322 ns ; w[2] ; r_reg[3] ; clk      ;
; N/A           ; None        ; -2.322 ns ; w[2] ; r_reg[2] ; clk      ;
; N/A           ; None        ; -2.322 ns ; w[2] ; r_reg[1] ; clk      ;
; N/A           ; None        ; -2.322 ns ; w[2] ; r_reg[0] ; clk      ;
; N/A           ; None        ; -2.322 ns ; w[2] ; r_reg[4] ; clk      ;
; N/A           ; None        ; -2.538 ns ; w[3] ; r_reg[3] ; clk      ;
; N/A           ; None        ; -2.538 ns ; w[3] ; r_reg[2] ; clk      ;
; N/A           ; None        ; -2.538 ns ; w[3] ; r_reg[1] ; clk      ;
; N/A           ; None        ; -2.538 ns ; w[3] ; r_reg[0] ; clk      ;
; N/A           ; None        ; -2.538 ns ; w[3] ; r_reg[4] ; clk      ;
; N/A           ; None        ; -2.583 ns ; d[3] ; r_reg[3] ; clk      ;
; N/A           ; None        ; -2.583 ns ; d[3] ; r_reg[2] ; clk      ;
; N/A           ; None        ; -2.583 ns ; d[3] ; r_reg[1] ; clk      ;
; N/A           ; None        ; -2.583 ns ; d[3] ; r_reg[0] ; clk      ;
; N/A           ; None        ; -2.583 ns ; d[3] ; r_reg[4] ; clk      ;
; N/A           ; None        ; -2.634 ns ; w[0] ; r_reg[3] ; clk      ;
; N/A           ; None        ; -2.634 ns ; w[0] ; r_reg[2] ; clk      ;
; N/A           ; None        ; -2.634 ns ; w[0] ; r_reg[1] ; clk      ;
; N/A           ; None        ; -2.634 ns ; w[0] ; r_reg[0] ; clk      ;
; N/A           ; None        ; -2.634 ns ; w[0] ; r_reg[4] ; clk      ;
; N/A           ; None        ; -2.976 ns ; w[1] ; r_reg[3] ; clk      ;
; N/A           ; None        ; -2.976 ns ; w[1] ; r_reg[2] ; clk      ;
; N/A           ; None        ; -2.976 ns ; w[1] ; r_reg[1] ; clk      ;
; N/A           ; None        ; -2.976 ns ; w[1] ; r_reg[0] ; clk      ;
; N/A           ; None        ; -2.976 ns ; w[1] ; r_reg[4] ; clk      ;
+---------------+-------------+-----------+------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Tue Oct 14 14:38:11 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ppg -c ppg --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "buf_next" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 380.08 MHz between source register "r_reg[0]" and destination register "r_reg[3]"
    Info: fmax restricted to clock pin edge rate 2.631 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.204 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X43_Y13_N15; Fanout = 6; REG Node = 'r_reg[0]'
            Info: 2: + IC(0.557 ns) + CELL(0.178 ns) = 0.735 ns; Loc. = LCCOMB_X43_Y13_N4; Fanout = 1; COMB Node = 'Equal0~31'
            Info: 3: + IC(0.296 ns) + CELL(0.322 ns) = 1.353 ns; Loc. = LCCOMB_X43_Y13_N6; Fanout = 5; COMB Node = 'Equal0~32'
            Info: 4: + IC(0.271 ns) + CELL(0.580 ns) = 2.204 ns; Loc. = LCFF_X43_Y13_N21; Fanout = 7; REG Node = 'r_reg[3]'
            Info: Total cell delay = 1.080 ns ( 49.00 % )
            Info: Total interconnect delay = 1.124 ns ( 51.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.868 ns
                Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.002 ns) + CELL(0.602 ns) = 2.868 ns; Loc. = LCFF_X43_Y13_N21; Fanout = 7; REG Node = 'r_reg[3]'
                Info: Total cell delay = 1.628 ns ( 56.76 % )
                Info: Total interconnect delay = 1.240 ns ( 43.24 % )
            Info: - Longest clock path from clock "clk" to source register is 2.868 ns
                Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.002 ns) + CELL(0.602 ns) = 2.868 ns; Loc. = LCFF_X43_Y13_N15; Fanout = 6; REG Node = 'r_reg[0]'
                Info: Total cell delay = 1.628 ns ( 56.76 % )
                Info: Total interconnect delay = 1.240 ns ( 43.24 % )
        Info: + Micro clock to output delay of source is 0.277 ns
        Info: + Micro setup delay of destination is -0.038 ns
Info: tsu for register "r_reg[3]" (data pin = "w[1]", clock pin = "clk") is 4.176 ns
    Info: + Longest pin to register delay is 7.082 ns
        Info: 1: + IC(0.000 ns) + CELL(1.006 ns) = 1.006 ns; Loc. = PIN_U12; Fanout = 2; PIN Node = 'w[1]'
        Info: 2: + IC(2.275 ns) + CELL(0.517 ns) = 3.798 ns; Loc. = LCCOMB_X42_Y13_N20; Fanout = 2; COMB Node = 'Add1~63'
        Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 3.878 ns; Loc. = LCCOMB_X42_Y13_N22; Fanout = 2; COMB Node = 'Add1~65'
        Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 3.958 ns; Loc. = LCCOMB_X42_Y13_N24; Fanout = 1; COMB Node = 'Add1~67'
        Info: 5: + IC(0.000 ns) + CELL(0.458 ns) = 4.416 ns; Loc. = LCCOMB_X42_Y13_N26; Fanout = 2; COMB Node = 'Add1~68'
        Info: 6: + IC(0.826 ns) + CELL(0.512 ns) = 5.754 ns; Loc. = LCCOMB_X43_Y13_N26; Fanout = 2; COMB Node = 'LessThan1~249'
        Info: 7: + IC(0.299 ns) + CELL(0.178 ns) = 6.231 ns; Loc. = LCCOMB_X43_Y13_N6; Fanout = 5; COMB Node = 'Equal0~32'
        Info: 8: + IC(0.271 ns) + CELL(0.580 ns) = 7.082 ns; Loc. = LCFF_X43_Y13_N21; Fanout = 7; REG Node = 'r_reg[3]'
        Info: Total cell delay = 3.411 ns ( 48.16 % )
        Info: Total interconnect delay = 3.671 ns ( 51.84 % )
    Info: + Micro setup delay of destination is -0.038 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.868 ns
        Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.002 ns) + CELL(0.602 ns) = 2.868 ns; Loc. = LCFF_X43_Y13_N21; Fanout = 7; REG Node = 'r_reg[3]'
        Info: Total cell delay = 1.628 ns ( 56.76 % )
        Info: Total interconnect delay = 1.240 ns ( 43.24 % )
Info: tco from clock "clk" to destination pin "pwm_pulse" through register "buf_reg" is 9.148 ns
    Info: + Longest clock path from clock "clk" to source register is 2.867 ns
        Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.001 ns) + CELL(0.602 ns) = 2.867 ns; Loc. = LCFF_X42_Y13_N1; Fanout = 1; REG Node = 'buf_reg'
        Info: Total cell delay = 1.628 ns ( 56.78 % )
        Info: Total interconnect delay = 1.239 ns ( 43.22 % )
    Info: + Micro clock to output delay of source is 0.277 ns
    Info: + Longest register to pin delay is 6.004 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X42_Y13_N1; Fanout = 1; REG Node = 'buf_reg'
        Info: 2: + IC(2.998 ns) + CELL(3.006 ns) = 6.004 ns; Loc. = PIN_A13; Fanout = 0; PIN Node = 'pwm_pulse'
        Info: Total cell delay = 3.006 ns ( 50.07 % )
        Info: Total interconnect delay = 2.998 ns ( 49.93 % )
Info: th for register "r_reg[3]" (data pin = "d[2]", clock pin = "clk") is -1.451 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.868 ns
        Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.002 ns) + CELL(0.602 ns) = 2.868 ns; Loc. = LCFF_X43_Y13_N21; Fanout = 7; REG Node = 'r_reg[3]'
        Info: Total cell delay = 1.628 ns ( 56.76 % )
        Info: Total interconnect delay = 1.240 ns ( 43.24 % )
    Info: + Micro hold delay of destination is 0.286 ns
    Info: - Shortest pin to register delay is 4.605 ns
        Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_M22; Fanout = 6; PIN Node = 'd[2]'
        Info: 2: + IC(1.151 ns) + CELL(0.544 ns) = 2.731 ns; Loc. = LCCOMB_X42_Y13_N22; Fanout = 2; COMB Node = 'Add1~64'
        Info: 3: + IC(0.532 ns) + CELL(0.491 ns) = 3.754 ns; Loc. = LCCOMB_X43_Y13_N6; Fanout = 5; COMB Node = 'Equal0~32'
        Info: 4: + IC(0.271 ns) + CELL(0.580 ns) = 4.605 ns; Loc. = LCFF_X43_Y13_N21; Fanout = 7; REG Node = 'r_reg[3]'
        Info: Total cell delay = 2.651 ns ( 57.57 % )
        Info: Total interconnect delay = 1.954 ns ( 42.43 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 127 megabytes
    Info: Processing ended: Tue Oct 14 14:38:14 2008
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:01