📄 ppg.sta.rpt
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+-------------------------------+
; Fast Model Hold Summary ;
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
; clk ; 0.255 ; 0.000 ;
+-------+-------+---------------+
-------------------------------
; Fast Model Recovery Summary ;
-------------------------------
No paths to report.
------------------------------
; Fast Model Removal Summary ;
------------------------------
No paths to report.
+-------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width ;
+--------+--------------+----------------+------------------+-------+------------+----------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+------------------+-------+------------+----------+
; -1.380 ; 1.000 ; 2.380 ; Port Rate ; clk ; Rise ; clk ;
; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; buf_reg ;
; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; buf_reg ;
; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; r_reg[0] ;
; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; r_reg[0] ;
; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; r_reg[1] ;
; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; r_reg[1] ;
; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; r_reg[2] ;
; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; r_reg[2] ;
; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; r_reg[3] ;
; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; r_reg[3] ;
; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; r_reg[4] ;
; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; r_reg[4] ;
+--------+--------------+----------------+------------------+-------+------------+----------+
+-----------------------------------------------------------------------+
; Setup Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; d[*] ; clk ; 0.842 ; 0.842 ; Rise ; clk ;
; d[0] ; clk ; 0.659 ; 0.659 ; Rise ; clk ;
; d[1] ; clk ; 0.634 ; 0.634 ; Rise ; clk ;
; d[2] ; clk ; 0.596 ; 0.596 ; Rise ; clk ;
; d[3] ; clk ; 0.842 ; 0.842 ; Rise ; clk ;
; w[*] ; clk ; 1.109 ; 1.109 ; Rise ; clk ;
; w[0] ; clk ; 0.975 ; 0.975 ; Rise ; clk ;
; w[1] ; clk ; 1.109 ; 1.109 ; Rise ; clk ;
; w[2] ; clk ; 0.971 ; 0.971 ; Rise ; clk ;
; w[3] ; clk ; 0.838 ; 0.838 ; Rise ; clk ;
+-----------+------------+-------+-------+------------+-----------------+
+-------------------------------------------------------------------------+
; Hold Times ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; d[*] ; clk ; -0.016 ; -0.016 ; Rise ; clk ;
; d[0] ; clk ; -0.184 ; -0.184 ; Rise ; clk ;
; d[1] ; clk ; -0.159 ; -0.159 ; Rise ; clk ;
; d[2] ; clk ; -0.016 ; -0.016 ; Rise ; clk ;
; d[3] ; clk ; -0.480 ; -0.480 ; Rise ; clk ;
; w[*] ; clk ; -0.393 ; -0.393 ; Rise ; clk ;
; w[0] ; clk ; -0.500 ; -0.500 ; Rise ; clk ;
; w[1] ; clk ; -0.634 ; -0.634 ; Rise ; clk ;
; w[2] ; clk ; -0.393 ; -0.393 ; Rise ; clk ;
; w[3] ; clk ; -0.474 ; -0.474 ; Rise ; clk ;
+-----------+------------+--------+--------+------------+-----------------+
+-----------------------------------------------------------------------+
; Clock to Output Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; pwm_pulse ; clk ; 4.680 ; 4.680 ; Rise ; clk ;
+-----------+------------+-------+-------+------------+-----------------+
+-----------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; pwm_pulse ; clk ; 4.680 ; 4.680 ; Rise ; clk ;
+-----------+------------+-------+-------+------------+-----------------+
+------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+------------------+--------+-------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+--------+-------+----------+---------+---------------------+
; Worst-case Slack ; -1.443 ; 0.0 ; 0.0 ; 0.0 ; -1.631 ;
; clk ; -1.443 ; 0.255 ; N/A ; N/A ; -1.631 ;
; Design-wide TNS ; -7.215 ; 0.0 ; 0.0 ; 0.0 ; N/A ;
; clk ; -7.215 ; 0.000 ; N/A ; N/A ; N/A ;
+------------------+--------+-------+----------+---------+---------------------+
+-------------------------------------------------------------------+
; Setup Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; clk ; clk ; 40 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+-------------------------------------------------------------------+
; Hold Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; clk ; clk ; 40 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design.
---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design.
+------------------------------------------------+
; Unconstrained Paths ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 9 ; 9 ;
; Unconstrained Input Port Paths ; 54 ; 54 ;
; Unconstrained Output Ports ; 1 ; 1 ;
; Unconstrained Output Port Paths ; 1 ; 1 ;
+---------------------------------+-------+------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
Info: Processing started: Tue Oct 14 14:35:47 2008
Info: Command: quartus_sta ppg -c ppg
Info: qsta_default_script.tcl version: #3
Warning: Timing Analysis is analyzing one or more combinational loops as latches
Warning: Node "buf_next|combout" is a latch
Critical Warning: Synopsys Design Constraints File file not found: 'ppg.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info: Deriving Clocks
Info: create_clock -period 1.000 -name clk clk
Info: Analyzing Slow Model
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -1.443
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: -1.443 -7.215 clk
Info: Worst-case hold slack is 0.651
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: 0.651 0.000 clk
Info: No recovery paths to report
Info: No removal paths to report
Critical Warning: Found minimum pulse width or period violations. See Report Minimum Pulse Width for details.
Info: Analyzing Fast Model
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -0.032
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: -0.032 -0.160 clk
Info: Worst-case hold slack is 0.255
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: 0.255 0.000 clk
Info: No recovery paths to report
Info: No removal paths to report
Critical Warning: Found minimum pulse width or period violations. See Report Minimum Pulse Width for details.
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings
Info: Peak virtual memory: 129 megabytes
Info: Processing ended: Tue Oct 14 14:35:51 2008
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:01
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