📄 ppg.sta.rpt
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TimeQuest Timing Analyzer report for ppg
Tue Oct 14 14:35:52 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Clocks
4. Slow Model Fmax Summary
5. Slow Model Setup Summary
6. Slow Model Hold Summary
7. Slow Model Recovery Summary
8. Slow Model Removal Summary
9. Slow Model Minimum Pulse Width
10. Setup Times
11. Hold Times
12. Clock to Output Times
13. Minimum Clock to Output Times
14. Fast Model Setup Summary
15. Fast Model Hold Summary
16. Fast Model Recovery Summary
17. Fast Model Removal Summary
18. Fast Model Minimum Pulse Width
19. Setup Times
20. Hold Times
21. Clock to Output Times
22. Minimum Clock to Output Times
23. Multicorner Timing Analysis Summary
24. Setup Transfers
25. Hold Transfers
26. Report TCCS
27. Report RSKM
28. Unconstrained Paths
29. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+--------------------------------------------------+
; Quartus II Version ; Version 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name ; ppg ;
; Device Family ; Cyclone II ;
; Device Name ; EP2C20F484C7 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Unavailable ;
+--------------------+--------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk } ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+-----------------------------------------------------------------------------------------------------------+
; Slow Model Fmax Summary ;
+------------+-----------------+------------+---------------------------------------------------------------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+------------+---------------------------------------------------------------+
; 409.33 MHz ; 380.08 MHz ; clk ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+--------------------------------+
; Slow Model Setup Summary ;
+-------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+
; clk ; -1.443 ; -7.215 ;
+-------+--------+---------------+
+-------------------------------+
; Slow Model Hold Summary ;
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
; clk ; 0.651 ; 0.000 ;
+-------+-------+---------------+
-------------------------------
; Slow Model Recovery Summary ;
-------------------------------
No paths to report.
------------------------------
; Slow Model Removal Summary ;
------------------------------
No paths to report.
+-------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width ;
+--------+--------------+----------------+------------------+-------+------------+----------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+------------------+-------+------------+----------+
; -1.631 ; 1.000 ; 2.631 ; Port Rate ; clk ; Rise ; clk ;
; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; buf_reg ;
; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; buf_reg ;
; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; r_reg[0] ;
; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; r_reg[0] ;
; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; r_reg[1] ;
; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; r_reg[1] ;
; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; r_reg[2] ;
; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; r_reg[2] ;
; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; r_reg[3] ;
; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; r_reg[3] ;
; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; r_reg[4] ;
; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; r_reg[4] ;
+--------+--------------+----------------+------------------+-------+------------+----------+
+-----------------------------------------------------------------------+
; Setup Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; d[*] ; clk ; 3.534 ; 3.534 ; Rise ; clk ;
; d[0] ; clk ; 3.186 ; 3.186 ; Rise ; clk ;
; d[1] ; clk ; 3.079 ; 3.079 ; Rise ; clk ;
; d[2] ; clk ; 3.002 ; 3.002 ; Rise ; clk ;
; d[3] ; clk ; 3.534 ; 3.534 ; Rise ; clk ;
; w[*] ; clk ; 4.176 ; 4.176 ; Rise ; clk ;
; w[0] ; clk ; 3.834 ; 3.834 ; Rise ; clk ;
; w[1] ; clk ; 4.176 ; 4.176 ; Rise ; clk ;
; w[2] ; clk ; 3.874 ; 3.874 ; Rise ; clk ;
; w[3] ; clk ; 3.485 ; 3.485 ; Rise ; clk ;
+-----------+------------+-------+-------+------------+-----------------+
+-------------------------------------------------------------------------+
; Hold Times ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; d[*] ; clk ; -1.451 ; -1.451 ; Rise ; clk ;
; d[0] ; clk ; -1.986 ; -1.986 ; Rise ; clk ;
; d[1] ; clk ; -1.879 ; -1.879 ; Rise ; clk ;
; d[2] ; clk ; -1.451 ; -1.451 ; Rise ; clk ;
; d[3] ; clk ; -2.583 ; -2.583 ; Rise ; clk ;
; w[*] ; clk ; -2.322 ; -2.322 ; Rise ; clk ;
; w[0] ; clk ; -2.634 ; -2.634 ; Rise ; clk ;
; w[1] ; clk ; -2.976 ; -2.976 ; Rise ; clk ;
; w[2] ; clk ; -2.322 ; -2.322 ; Rise ; clk ;
; w[3] ; clk ; -2.538 ; -2.538 ; Rise ; clk ;
+-----------+------------+--------+--------+------------+-----------------+
+-----------------------------------------------------------------------+
; Clock to Output Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; pwm_pulse ; clk ; 9.148 ; 9.148 ; Rise ; clk ;
+-----------+------------+-------+-------+------------+-----------------+
+-----------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; pwm_pulse ; clk ; 9.148 ; 9.148 ; Rise ; clk ;
+-----------+------------+-------+-------+------------+-----------------+
+--------------------------------+
; Fast Model Setup Summary ;
+-------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+
; clk ; -0.032 ; -0.160 ;
+-------+--------+---------------+
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