median.map.summary

来自「用verilog编辑的中值滤波器！语言旁表有注释方便理解！」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Sun Aug 17 16:01:36 2008
Quartus II Version : 7.2 Build 175 11/20/2007 SP 1 SJ Full Version
Revision Name : median
Top-level Entity Name : median
Family : Cyclone II
Total logic elements : 584
    Total combinational functions : 584
    Dedicated logic registers : 334
Total registers : 334
Total pins : 95
Total virtual pins : 0
Total memory bits : 41,472
Embedded Multiplier 9-bit elements : 1
Total PLLs : 0