prev_cmp_median.qmsg

用verilog编辑的中值滤波器！语言旁表有注释方便理解！

{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|median\|img_y " "Info: Encoding result for state machine \"\|median\|img_y\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "img_y.00 " "Info: Encoded state bit \"img_y.00\"" {  } { { "median.v" "" { Text "I:/panjian9/median.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "img_y.10 " "Info: Encoded state bit \"img_y.10\"" {  } { { "median.v" "" { Text "I:/panjian9/median.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "img_y.01 " "Info: Encoded state bit \"img_y.01\"" {  } { { "median.v" "" { Text "I:/panjian9/median.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|median\|img_y.00 000 " "Info: State \"\|median\|img_y.00\" uses code string \"000\"" {  } { { "median.v" "" { Text "I:/panjian9/median.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|median\|img_y.01 101 " "Info: State \"\|median\|img_y.01\" uses code string \"101\"" {  } { { "median.v" "" { Text "I:/panjian9/median.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|median\|img_y.10 110 " "Info: State \"\|median\|img_y.10\" uses code string \"110\"" {  } { { "median.v" "" { Text "I:/panjian9/median.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "median.v" "" { Text "I:/panjian9/median.v" 16 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "3 " "Info: Inferred 3 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "ram:r1\|mem~0 " "Info: Inferred altsyncram megafunction from the following design logic: \"ram:r1\|mem~0\" " { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE SINGLE_PORT " "Info: Parameter OPERATION_MODE set to SINGLE_PORT" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Info: Parameter WIDTH_A set to 8" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 11 " "Info: Parameter WIDTHAD_A set to 11" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 1728 " "Info: Parameter NUMWORDS_A set to 1728" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter OUTDATA_REG_A set to UNREGISTERED" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Info: Parameter ADDRESS_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_A NONE " "Info: Parameter OUTDATA_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Info: Parameter INDATA_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Info: Parameter WRCONTROL_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "RAM_BLOCK_TYPE AUTO " "Info: Parameter RAM_BLOCK_TYPE set to AUTO" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0}  } { { "median.v" "mem~0" { Text "I:/panjian9/median.v" 429 -1 0 } }  } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "" 0} { "Info" "IOPT_ALTSYNCRAM_INFERRED" "ram:r2\|mem~0 " "Info: Inferred altsyncram megafunction from the following design logic: \"ram:r2\|mem~0\" " { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE SINGLE_PORT " "Info: Parameter OPERATION_MODE set to SINGLE_PORT" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Info: Parameter WIDTH_A set to 8" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 11 " "Info: Parameter WIDTHAD_A set to 11" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 1728 " "Info: Parameter NUMWORDS_A set to 1728" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter OUTDATA_REG_A set to UNREGISTERED" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Info: Parameter ADDRESS_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_A NONE " "Info: Parameter OUTDATA_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Info: Parameter INDATA_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Info: Parameter WRCONTROL_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "RAM_BLOCK_TYPE AUTO " "Info: Parameter RAM_BLOCK_TYPE set to AUTO" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0}  } { { "median.v" "mem~0" { Text "I:/panjian9/median.v" 429 -1 0 } }  } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "" 0} { "Info" "IOPT_ALTSYNCRAM_INFERRED" "ram:r3\|mem~0 " "Info: Inferred altsyncram megafunction from the following design logic: \"ram:r3\|mem~0\" " { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE SINGLE_PORT " "Info: Parameter OPERATION_MODE set to SINGLE_PORT" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Info: Parameter WIDTH_A set to 8" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 11 " "Info: Parameter WIDTHAD_A set to 11" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 1728 " "Info: Parameter NUMWORDS_A set to 1728" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter OUTDATA_REG_A set to UNREGISTERED" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Info: Parameter ADDRESS_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_A NONE " "Info: Parameter OUTDATA_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Info: Parameter INDATA_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Info: Parameter WRCONTROL_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "RAM_BLOCK_TYPE AUTO " "Info: Parameter RAM_BLOCK_TYPE set to AUTO" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0}  } { { "median.v" "mem~0" { Text "I:/panjian9/median.v" 429 -1 0 } }  } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "" 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult0 lpm_mult " "Info: Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult0\"" {  } { { "median.v" "Mult0" { Text "I:/panjian9/median.v" 367 -1 0 } }  } 0 0 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "ram:r1\|altsyncram:mem_rtl_0 " "Info: Elaborated megafunction instantiation \"ram:r1\|altsyncram:mem_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_hd61.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_hd61.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_hd61 " "Info: Found entity 1: altsyncram_hd61" {  } { { "db/altsyncram_hd61.tdf" "" { Text "I:/panjian9/db/altsyncram_hd61.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/72/quartus/libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/72/quartus/libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" {  } { { "lpm_mult.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_mult.tdf" 284 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult0 " "Info: Elaborated megafunction instantiation \"lpm_mult:Mult0\"" {  } { { "median.v" "" { Text "I:/panjian9/median.v" 367 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_2s01.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_2s01.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_2s01 " "Info: Found entity 1: mult_2s01" {  } { { "db/mult_2s01.tdf" "" { Text "I:/panjian9/db/mult_2s01.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "median.v" "" { Text "I:/panjian9/median.v" 35 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}