median.cbx.xml

用verilog编辑的中值滤波器！语言旁表有注释方便理解！

<?xml version="1.0" ?>
<LOG_ROOT>
	<PROJECT NAME="median">
		<CBX_INST_ENTRY INSTANCE_NAME="|median|lpm_mult:Mult0" CBX_FILE_NAME="mult_2s01.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|median|ram:r1|altsyncram:mem_rtl_0" CBX_FILE_NAME="altsyncram_hd61.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|median|ram:r2|altsyncram:mem_rtl_1" CBX_FILE_NAME="altsyncram_hd61.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|median|ram:r3|altsyncram:mem_rtl_2" CBX_FILE_NAME="altsyncram_hd61.tdf"/>
	</PROJECT>
</LOG_ROOT>