median.vo

用verilog编辑的中值滤波器！语言旁表有注释方便理解！

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version"

// DATE "08/17/2008 16:02:09"

// 
// Device: Altera EP2C20F484C7 Package FBGA484
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module median (
	clk,
	reset,
	load,
	din,
	mult,
	dout,
	over,
	a3,
	b3,
	c3,
	a2,
	b2,
	c2,
	a1,
	b1,
	c1);
input 	clk;
input 	reset;
input 	load;
input 	[7:0] din;
input 	[2:0] mult;
output 	[7:0] dout;
output 	over;
output 	[7:0] a3;
output 	[7:0] b3;
output 	[7:0] c3;
output 	[7:0] a2;
output 	[7:0] b2;
output 	[7:0] c2;
output 	[7:0] a1;
output 	[7:0] b1;
output 	[7:0] c1;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("median_v.sdo");
// synopsys translate_on

wire \Mult0|auto_generated|mac_out2~0 ;
wire \Mult0|auto_generated|mac_out2~1 ;
wire \Mult0|auto_generated|mac_out2~2 ;
wire \Mult0|auto_generated|mac_out2~3 ;
wire \Mult0|auto_generated|mac_out2~4 ;
wire \Mult0|auto_generated|mac_out2~5 ;
wire \Mult0|auto_generated|mac_out2~6 ;
wire \img_x[6]~905_combout ;
wire \LessThan28~105_cout ;
wire \LessThan28~107_cout ;
wire \LessThan28~109_cout ;
wire \LessThan28~111_cout ;
wire \LessThan28~113_cout ;
wire \LessThan28~115_cout ;
wire \LessThan28~117_cout ;
wire \LessThan28~118_combout ;
wire \q_min[0]~163_combout ;
wire \q_min[1]~165_combout ;
wire \q_min[2]~167_combout ;
wire \q_min[5]~173_combout ;
wire \LessThan3~105_cout ;
wire \LessThan3~107_cout ;
wire \LessThan3~109_cout ;
wire \LessThan3~111_cout ;
wire \LessThan3~113_cout ;
wire \LessThan3~115_cout ;
wire \LessThan3~117_cout ;
wire \LessThan3~118_combout ;
wire \d2[0]~188_combout ;
wire \d2[0]~189 ;
wire \d2[1]~190_combout ;
wire \d2[1]~191 ;
wire \d2[2]~192_combout ;
wire \d2[2]~193 ;
wire \d2[3]~194_combout ;
wire \d2[3]~195 ;
wire \d2[4]~196_combout ;
wire \d2[4]~197 ;
wire \d2[5]~198_combout ;
wire \d2[5]~199 ;
wire \d2[6]~200_combout ;
wire \d2[6]~201 ;
wire \d2[7]~202_combout ;
wire \d3[1]~179_combout ;
wire \d3[4]~185_combout ;
wire \d3[5]~187_combout ;
wire \d0[0]~1145_combout ;
wire \d0[4]~1153_combout ;
wire \d0[5]~1155_combout ;
wire \d1[1]~179_combout ;
wire \d1[6]~189_combout ;
wire \mid[0]~1111_combout ;
wire \c_mid[0]~431_combout ;
wire \c_mid[3]~428_combout ;
wire \a_mid[2]~1173_combout ;
wire \a3[0]~498_combout ;
wire \we0~regout ;
wire \we2~regout ;
wire \we1~regout ;
wire \img_y.00~regout ;
wire \we0~60_combout ;
wire \img_y.10~regout ;
wire \we2~67_combout ;
wire \img_y.01~regout ;
wire \we1~66_combout ;
wire \we1~67_combout ;
wire \sum2~regout ;
wire \Add11~131_combout ;
wire \img_y.01~168_combout ;
wire \cur_state.s4~regout ;
wire \LessThan7~105_combout ;
wire \LessThan7~106_combout ;
wire \LessThan7~107_combout ;
wire \LessThan8~106_combout ;
wire \LessThan5~106_combout ;
wire \Selector107~14_combout ;
wire \Selector108~14_combout ;
wire \cur_state~868_combout ;
wire \Add5~273_combout ;
wire \Add5~274_combout ;
wire \Add5~275_combout ;
wire \Add5~276_combout ;
wire \Add5~277_combout ;
wire \Add5~278_combout ;
wire \Add5~279_combout ;
wire \Add5~280_combout ;
wire \Add5~281_combout ;
wire \Add5~282_combout ;
wire \Add5~283_combout ;
wire \Add5~284_combout ;
wire \Add5~285_combout ;
wire \Add5~286_combout ;
wire \Add5~287_combout ;
wire \Add5~288_combout ;
wire \Add7~274_combout ;
wire \Add7~275_combout ;
wire \Add7~278_combout ;
wire \Add7~279_combout ;
wire \Add7~282_combout ;
wire \Add7~284_combout ;
wire \Add7~286_combout ;
wire \Add1~274_combout ;
wire \Add1~275_combout ;
wire \Add1~277_combout ;
wire \Add1~279_combout ;
wire \Add1~282_combout ;
wire \Add1~283_combout ;
wire \Add1~285_combout ;
wire \Add1~287_combout ;
wire \Add3~274_combout ;
wire \Add3~276_combout ;
wire \Add3~277_combout ;
wire \Add3~280_combout ;
wire \Add3~282_combout ;
wire \Add3~284_combout ;
wire \Add3~285_combout ;
wire \Add3~288_combout ;
wire \Selector102~14_combout ;
wire \Selector73~14_combout ;
wire \Selector76~14_combout ;
wire \Selector61~14_combout ;
wire \img_y~180_combout ;
wire \img_y.00~11_combout ;
wire \img_y.10~feeder_combout ;
wire \clk~combout ;
wire \clk~clkctrl_outclk ;
wire \Add12~132_combout ;
wire \pix~1122_combout ;
wire \reset~combout ;
wire \reset~clkctrl_outclk ;
wire \en~782_combout ;
wire \en~783_combout ;
wire \run_edge~regout ;
wire \load~combout ;
wire \always0~77_combout ;
wire \img_y.01~167_combout ;
wire \img_x[0]~893_combout ;
wire \img_x[10]~892_combout ;
wire \img_x[0]~894 ;
wire \img_x[1]~895_combout ;
wire \img_x[1]~896 ;
wire \img_x[2]~897_combout ;
wire \img_x[2]~898 ;
wire \img_x[3]~900 ;
wire \img_x[4]~901_combout ;
wire \img_x[4]~902 ;
wire \img_x[5]~904 ;
wire \img_x[6]~906 ;
wire \img_x[7]~907_combout ;
wire \img_x[7]~908 ;
wire \img_x[8]~909_combout ;
wire \img_x[8]~910 ;
wire \img_x[9]~911_combout ;
wire \LessThan0~130_combout ;
wire \img_x[9]~912 ;
wire \img_x[10]~913_combout ;
wire \LessThan0~131_combout ;
wire \state.s1~167_combout ;
wire \state.s1~regout ;
wire \cur_state~857_combout ;
wire \pix[9]~1125_combout ;
wire \Add12~133 ;
wire \Add12~135 ;
wire \Add12~136_combout ;
wire \Add12~134_combout ;
wire \Equal0~127_combout ;
wire \Add12~137 ;
wire \Add12~139 ;
wire \Add12~140_combout ;
wire \Add12~141 ;
wire \Add12~143 ;
wire \Add12~144_combout ;
wire \pix~1123_combout ;
wire \Add12~145 ;
wire \Add12~146_combout ;
wire \pix~1121_combout ;
wire \Add12~147 ;
wire \Add12~148_combout ;
wire \Add12~149 ;
wire \Add12~150_combout ;
wire \pix~1120_combout ;
wire \Equal0~125_combout ;
wire \pix[9]~1119_combout ;
wire \Add12~151 ;
wire \Add12~152_combout ;
wire \pix~1124_combout ;
wire \Add12~142_combout ;
wire \Equal0~126_combout ;
wire \Equal0~128_combout ;
wire \cur_state~854_combout ;
wire \cur_state~855_combout ;
wire \cur_state.s14~regout ;
wire \cur_state~856_combout ;
wire \cur_state.s15~regout ;
wire \en~784_combout ;
wire \en~regout ;
wire \always0~78_combout ;
wire \cur_state~866_combout ;
wire \cur_state.s5~regout ;
wire \cur_state~864_combout ;
wire \cur_state.s6~regout ;
wire \wrdata[6]~feeder_combout ;
wire \wrdata[0]~807_combout ;
wire \addr~863_combout ;
wire \addr[0]~864_combout ;
wire \addr[0]~865_combout ;
wire \addr~866_combout ;
wire \addr~867_combout ;
wire \Add12~138_combout ;
wire \img_x[3]~899_combout ;
wire \addr~868_combout ;
wire \addr~869_combout ;
wire \img_x[5]~903_combout ;
wire \addr~870_combout ;
wire \addr~871_combout ;
wire \addr~872_combout ;
wire \addr~873_combout ;
wire \addr~874_combout ;
wire \addr~875_combout ;
wire \wrdata[7]~feeder_combout ;
wire \a3[6]~414_combout ;
wire \Selector0~135_combout ;
wire \cur_state~858_combout ;
wire \cur_state~859_combout ;
wire \cur_state.s1~regout ;
wire \cur_state.s0~129_combout ;
wire \Selector0~136_combout ;
wire \piy.00000000000~regout ;
wire \Selector1~133_combout ;
wire \cur_state~860_combout ;
wire \cur_state.s2~regout ;
wire \Selector1~134_combout ;
wire \Selector1~135_combout ;
wire \piy.00000000001~regout ;
wire \Selector2~143_combout ;
wire \Selector2~144_combout ;
wire \Selector2~145_combout ;
wire \piy.00000000010~regout ;
wire \c3[2]~537_combout ;
wire \cur_state~861_combout ;
wire \cur_state.s0~regout ;
wire \WideOr1~combout ;
wire \a3[0]~499_combout ;
wire \a3[6]~reg0_regout ;
wire \a2[0]~99_combout ;
wire \a2[6]~reg0_regout ;
wire \c3[2]~536_combout ;
wire \a3[7]~415_combout ;
wire \a3[7]~reg0_regout ;
wire \a2[7]~reg0_regout ;
wire \b3[7]~415_combout ;
wire \b3[7]~reg0_regout ;
wire \b2[7]~reg0_regout ;
wire \wrdata[4]~feeder_combout ;
wire \wrdata[5]~feeder_combout ;
wire \a3[5]~413_combout ;
wire \a3[5]~reg0_regout ;
wire \a2[5]~reg0_regout ;
wire \a3[4]~412_combout ;
wire \a3[4]~reg0_regout ;
wire \a2[4]~reg0_regout ;
wire \a3[3]~411_combout ;
wire \a3[3]~reg0_regout ;
wire \a2[3]~reg0_regout ;
wire \a3[2]~410_combout ;
wire \a3[2]~reg0_regout ;
wire \a2[2]~reg0_regout ;
wire \wrdata[1]~feeder_combout ;
wire \b3[1]~409_combout ;
wire \b3[1]~reg0_regout ;
wire \b2[1]~reg0_regout ;
wire \a3[0]~408_combout ;
wire \a3[0]~reg0_regout ;
wire \a2[0]~reg0_regout ;
wire \LessThan1~105_cout ;
wire \LessThan1~107_cout ;
wire \LessThan1~109_cout ;
wire \LessThan1~111_cout ;
wire \LessThan1~113_cout ;
wire \LessThan1~115_cout ;
wire \LessThan1~117_cout ;
wire \LessThan1~118_combout ;
wire \Add1~286_combout ;
wire \Add1~284_combout ;
wire \b3[4]~412_combout ;
wire \b3[4]~reg0_regout ;
wire \b2[4]~reg0_regout ;
wire \Add1~281_combout ;
wire \Add1~273_combout ;
wire \Add1~276_combout ;
wire \a3[1]~409_combout ;
wire \a3[1]~reg0_regout ;
wire \a2[1]~reg0_regout ;
wire \Add1~278_combout ;
wire \Add1~280_combout ;
wire \d0[0]~1146 ;
wire \d0[1]~1148 ;
wire \d0[2]~1150 ;
wire \d0[3]~1152 ;
wire \d0[4]~1154 ;
wire \d0[5]~1156 ;
wire \d0[6]~1157_combout ;
wire \cur_state~871_combout ;
wire \cur_state.s3~regout ;
wire \d2[7]~204_combout ;
wire \d0[3]~1151_combout ;
wire \d0[1]~1147_combout ;
wire \d0[2]~1149_combout ;
wire \LessThan5~105_combout ;
wire \Add1~288_combout ;
wire \d0[6]~1158 ;
wire \d0[7]~1159_combout ;
wire \LessThan5~107_combout ;
wire \sum2~20_combout ;
wire \sum0~regout ;
wire \b3[6]~414_combout ;
wire \b3[6]~reg0_regout ;
wire \b2[6]~reg0_regout ;
wire \b3[5]~413_combout ;
wire \b3[5]~reg0_regout ;
wire \b2[5]~reg0_regout ;
wire \b1[5]~reg0_regout ;
wire \b1[4]~reg0_regout ;
wire \b3[3]~411_combout ;
wire \b3[3]~reg0_regout ;
wire \b2[3]~reg0_regout ;
wire \b1[3]~reg0_regout ;
wire \b3[2]~410_combout ;
wire \b3[2]~reg0_regout ;
wire \b2[2]~reg0_regout ;
wire \b1[2]~reg0_regout ;
wire \b1[1]~reg0_regout ;
wire \b3[0]~408_combout ;
wire \b3[0]~reg0_regout ;
wire \b2[0]~reg0_regout ;
wire \b1[0]~reg0_regout ;
wire \LessThan2~105_cout ;
wire \LessThan2~107_cout ;
wire \LessThan2~109_cout ;
wire \LessThan2~111_cout ;
wire \LessThan2~113_cout ;
wire \LessThan2~115_cout ;
wire \LessThan2~117_cout ;
wire \LessThan2~118_combout ;
wire \Add3~281_combout ;
wire \Add3~273_combout ;
wire \Add3~275_combout ;
wire \Add3~278_combout ;
wire \Add3~279_combout ;
wire \d1[0]~178 ;
wire \d1[1]~180 ;